Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_io_meas.u_meas.u_sync_ref	100.00	100.00	100.00			100.00	100.00
tb.dut.u_io_div2_meas.u_meas.u_sync_ref	100.00	100.00	100.00			100.00	100.00
tb.dut.u_io_div4_meas.u_meas.u_sync_ref	100.00	100.00	100.00			100.00	100.00
tb.dut.u_main_meas.u_meas.u_sync_ref	100.00	100.00	100.00			100.00	100.00
tb.dut.u_usb_meas.u_meas.u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_div2_meas_ctrl_en_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_div2_meas_ctrl_shadowed_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_div4_meas_ctrl_en_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_div4_meas_ctrl_shadowed_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_main_meas_ctrl_en_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_main_meas_ctrl_shadowed_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_usb_meas_ctrl_en_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_usb_meas_ctrl_shadowed_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1264265519	434102	0	0
SrcPulseCheck_M	1098173602	432225	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1264265519	434102	0	0
T1	224386	285	0	0
T2	0	10	0	0
T3	0	20	0	0
T9	0	216	0	0
T10	0	388	0	0
T11	0	200	0	0
T12	0	198	0	0
T20	0	120	0	0
T28	0	170	0	0
T40	0	141	0	0
T41	0	10	0	0
T43	0	1	0	0
T51	0	272	0	0
T52	9529	0	0	0
T53	6880	0	0	0
T54	21366	0	0	0
T55	11578	0	0	0
T56	27449	0	0	0
T57	89843	0	0	0
T58	7371	0	0	0
T59	23836	0	0	0
T60	24445	0	0	0
T68	0	680	0	0
T69	0	320	0	0
T98	13992	2	0	0
T101	12752	2	0	0
T118	0	48	0	0
T120	14646	1	0	0
T121	8028	1	0	0
T122	14782	0	0	0
T123	5200	1	0	0
T124	2697	0	0	0
T125	16094	0	0	0
T144	19640	0	0	0
T145	10027	0	0	0
T146	5206	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098173602	432225	0	0
T1	52301	285	0	0
T2	0	10	0	0
T3	0	20	0	0
T9	0	216	0	0
T10	0	388	0	0
T11	0	200	0	0
T12	0	198	0	0
T20	0	120	0	0
T28	0	170	0	0
T40	0	141	0	0
T41	0	10	0	0
T43	0	1	0	0
T51	0	272	0	0
T52	3341	0	0	0
T53	4020	0	0	0
T54	9004	0	0	0
T55	6809	0	0	0
T56	8895	0	0	0
T57	38863	0	0	0
T58	4418	0	0	0
T59	7896	0	0	0
T60	7278	0	0	0
T68	0	680	0	0
T69	0	320	0	0
T98	12524	2	0	0
T101	26412	2	0	0
T118	0	48	0	0
T120	5964	1	0	0
T121	15200	1	0	0
T122	6392	0	0	0
T123	8868	1	0	0
T124	4978	0	0	0
T125	6444	0	0	0
T144	8330	0	0	0
T145	4062	0	0	0
T146	13054	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	72852934	10981	0	0
SrcPulseCheck_M	35689686	10981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72852934	10981	0	0
T1	52692	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	2367	0	0	0
T53	1445	0	0	0
T54	4976	0	0	0
T55	2430	0	0	0
T56	6826	0	0	0
T57	22618	0	0	0
T58	1551	0	0	0
T59	5711	0	0	0
T60	6180	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	10981	0	0
T1	12708	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	72852934	17206	0	0
SrcPulseCheck_M	35689686	17231	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72852934	17206	0	0
T1	52692	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	2367	0	0	0
T53	1445	0	0	0
T54	4976	0	0	0
T55	2430	0	0	0
T56	6826	0	0	0
T57	22618	0	0	0
T58	1551	0	0	0
T59	5711	0	0	0
T60	6180	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17231	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	17196	0	0
SrcPulseCheck_M	72852934	17209	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17196	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	72852934	17209	0	0
T1	52692	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	2367	0	0	0
T53	1445	0	0	0
T54	4976	0	0	0
T55	2430	0	0	0
T56	6826	0	0	0
T57	22618	0	0	0
T58	1551	0	0	0
T59	5711	0	0	0
T60	6180	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35501909	10981	0	0
SrcPulseCheck_M	35689686	10981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35501909	10981	0	0
T1	26313	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	1123	0	0	0
T53	710	0	0	0
T54	2476	0	0	0
T55	1189	0	0	0
T56	3353	0	0	0
T57	9177	0	0	0
T58	740	0	0	0
T59	3020	0	0	0
T60	3030	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	10981	0	0
T1	12708	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35501909	17095	0	0
SrcPulseCheck_M	35689686	17129	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35501909	17095	0	0
T1	26313	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	1123	0	0	0
T53	710	0	0	0
T54	2476	0	0	0
T55	1189	0	0	0
T56	3353	0	0	0
T57	9177	0	0	0
T58	740	0	0	0
T59	3020	0	0	0
T60	3030	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17129	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	17092	0	0
SrcPulseCheck_M	35501909	17103	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17092	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35501909	17103	0	0
T1	26313	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	1123	0	0	0
T53	710	0	0	0
T54	2476	0	0	0
T55	1189	0	0	0
T56	3353	0	0	0
T57	9177	0	0	0
T58	740	0	0	0
T59	3020	0	0	0
T60	3030	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	17750577	10981	0	0
SrcPulseCheck_M	35689686	10981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17750577	10981	0	0
T1	13157	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	562	0	0	0
T53	354	0	0	0
T54	1238	0	0	0
T55	594	0	0	0
T56	1676	0	0	0
T57	4588	0	0	0
T58	370	0	0	0
T59	1510	0	0	0
T60	1515	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	10981	0	0
T1	12708	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	17750577	17131	0	0
SrcPulseCheck_M	35689686	17155	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17750577	17131	0	0
T1	13157	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	562	0	0	0
T53	354	0	0	0
T54	1238	0	0	0
T55	594	0	0	0
T56	1676	0	0	0
T57	4588	0	0	0
T58	370	0	0	0
T59	1510	0	0	0
T60	1515	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17155	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	17127	0	0
SrcPulseCheck_M	17750577	17133	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17127	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	17750577	17133	0	0
T1	13157	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	562	0	0	0
T53	354	0	0	0
T54	1238	0	0	0
T55	594	0	0	0
T56	1676	0	0	0
T57	4588	0	0	0
T58	370	0	0	0
T59	1510	0	0	0
T60	1515	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	80538637	10981	0	0
SrcPulseCheck_M	35689686	10981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80538637	10981	0	0
T1	66890	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T54	5184	0	0	0
T55	2531	0	0	0
T56	7111	0	0	0
T57	23561	0	0	0
T58	1615	0	0	0
T59	5949	0	0	0
T60	6438	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	10981	0	0
T1	12708	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	80538637	17032	0	0
SrcPulseCheck_M	35689686	17048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80538637	17032	0	0
T1	66890	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T54	5184	0	0	0
T55	2531	0	0	0
T56	7111	0	0	0
T57	23561	0	0	0
T58	1615	0	0	0
T59	5949	0	0	0
T60	6438	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17048	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	17022	0	0
SrcPulseCheck_M	80538637	17035	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17022	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	80538637	17035	0	0
T1	66890	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T54	5184	0	0	0
T55	2531	0	0	0
T56	7111	0	0	0
T57	23561	0	0	0
T58	1615	0	0	0
T59	5949	0	0	0
T60	6438	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	38644480	10642	0	0
SrcPulseCheck_M	35689686	10981	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38644480	10642	0	0
T1	32108	10	0	0
T2	0	1	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	12	0	0
T28	0	17	0	0
T40	0	4	0	0
T41	0	1	0	0
T51	0	12	0	0
T52	1184	0	0	0
T53	722	0	0	0
T54	2489	0	0	0
T55	1215	0	0	0
T56	3413	0	0	0
T57	11310	0	0	0
T58	775	0	0	0
T59	2855	0	0	0
T60	3091	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	10981	0	0
T1	12708	10	0	0
T2	0	2	0	0
T3	0	4	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	24	0	0
T28	0	34	0	0
T40	0	4	0	0
T41	0	2	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	38644480	16936	0	0
SrcPulseCheck_M	35689686	17067	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38644480	16936	0	0
T1	32108	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	43	0	0
T28	0	65	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	1184	0	0	0
T53	722	0	0	0
T54	2489	0	0	0
T55	1215	0	0	0
T56	3413	0	0	0
T57	11310	0	0	0
T58	775	0	0	0
T59	2855	0	0	0
T60	3091	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	17067	0	0
T1	12708	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	48	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	16812	0	0
SrcPulseCheck_M	38644480	16950	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	16812	0	0
T1	12708	10	0	0
T2	0	3	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	42	0	0
T28	0	51	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	765	0	0	0
T53	1445	0	0	0
T54	2540	0	0	0
T55	2456	0	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	38644480	16950	0	0
T1	32108	10	0	0
T2	0	4	0	0
T3	0	8	0	0
T9	0	16	0	0
T10	0	28	0	0
T20	0	43	0	0
T28	0	68	0	0
T40	0	4	0	0
T41	0	4	0	0
T51	0	12	0	0
T52	1184	0	0	0
T53	722	0	0	0
T54	2489	0	0	0
T55	1215	0	0	0
T56	3413	0	0	0
T57	11310	0	0	0
T58	775	0	0	0
T59	2855	0	0	0
T60	3091	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T98 T101 T122 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T98,T101,T122
1	0	Covered	T98,T101,T122
1	1	Covered	T147,T148

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T98,T101,T122
1	0	Covered	T147,T148
1	1	Covered	T98,T101,T122

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	29	0	0
SrcPulseCheck_M	72852934	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	29	0	0
T98	6996	1	0	0
T101	6376	1	0	0
T122	7391	1	0	0
T124	2697	1	0	0
T125	8047	2	0	0
T126	7191	1	0	0
T145	10027	1	0	0
T149	14742	1	0	0
T150	4054	1	0	0
T151	3820	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	72852934	29	0	0
T98	13991	1	0	0
T101	27824	1	0	0
T122	7391	1	0	0
T124	10788	1	0	0
T125	7725	2	0	0
T126	7043	1	0	0
T145	9625	1	0	0
T149	14588	1	0	0
T150	7208	1	0	0
T151	15942	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T120 T121 T98 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T120,T121,T98
1	0	Covered	T120,T121,T98
1	1	Covered	T152,T153,T154

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T120,T121,T98
1	0	Covered	T152,T153,T154
1	1	Covered	T120,T121,T98

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	22	0	0
SrcPulseCheck_M	72852934	22	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	22	0	0
T98	6996	1	0	0
T120	7323	1	0	0
T121	4014	1	0	0
T122	7391	1	0	0
T125	8047	1	0	0
T144	9820	1	0	0
T150	4054	1	0	0
T151	3820	1	0	0
T152	3562	2	0	0
T155	8140	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	72852934	22	0	0
T98	13991	1	0	0
T120	7029	1	0	0
T121	16056	1	0	0
T122	7391	1	0	0
T125	7725	1	0	0
T144	9820	1	0	0
T150	7208	1	0	0
T151	15942	1	0	0
T152	14249	2	0	0
T155	7814	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T120 T121 T98 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T120,T121,T98
1	0	Covered	T120,T121,T98
1	1	Covered	T125,T155,T156

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T120,T121,T98
1	0	Covered	T125,T155,T156
1	1	Covered	T120,T121,T98

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	35	0	0
SrcPulseCheck_M	35501909	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	35	0	0
T98	6996	2	0	0
T101	6376	2	0	0
T120	7323	1	0	0
T121	4014	1	0	0
T122	7391	1	0	0
T123	2600	1	0	0
T124	2697	1	0	0
T125	8047	2	0	0
T144	9820	1	0	0
T146	2603	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35501909	35	0	0
T98	6262	2	0	0
T101	13206	2	0	0
T120	2982	1	0	0
T121	7600	1	0	0
T122	3196	1	0	0
T123	4434	1	0	0
T124	4978	1	0	0
T125	3222	2	0	0
T144	4165	1	0	0
T146	6527	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T120 T121 T98 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T120,T121,T98
1	0	Covered	T120,T121,T98
1	1	Covered	T120,T98,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T120,T121,T98
1	0	Covered	T120,T98,T125
1	1	Covered	T120,T121,T98

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	32	0	0
SrcPulseCheck_M	35501909	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	32	0	0
T98	6996	2	0	0
T101	6376	2	0	0
T120	7323	2	0	0
T121	4014	1	0	0
T122	7391	1	0	0
T123	2600	1	0	0
T125	8047	2	0	0
T144	9820	2	0	0
T145	10027	1	0	0
T146	2603	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35501909	32	0	0
T98	6262	2	0	0
T101	13206	2	0	0
T120	2982	2	0	0
T121	7600	1	0	0
T122	3196	1	0	0
T123	4434	1	0	0
T125	3222	2	0	0
T144	4165	2	0	0
T145	4062	1	0	0
T146	6527	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T121 T101 T122 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T121,T101,T122
1	0	Covered	T121,T101,T122
1	1	Covered	T124,T157,T158

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T121,T101,T122
1	0	Covered	T124,T157,T158
1	1	Covered	T121,T101,T122

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	28	0	0
SrcPulseCheck_M	17750577	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	28	0	0
T101	6376	1	0	0
T121	4014	1	0	0
T122	7391	1	0	0
T124	2697	2	0	0
T145	10027	1	0	0
T146	2603	1	0	0
T147	11916	2	0	0
T149	14742	1	0	0
T150	4054	1	0	0
T155	8140	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	17750577	28	0	0
T101	6602	1	0	0
T121	3799	1	0	0
T122	1597	1	0	0
T124	2486	2	0	0
T145	2035	1	0	0
T146	3265	1	0	0
T147	2399	2	0	0
T149	3264	1	0	0
T150	1581	1	0	0
T155	1816	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T123 T101 T122 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T123,T101,T122
1	0	Covered	T123,T101,T122
1	1	Covered	T122,T124,T147

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T123,T101,T122
1	0	Covered	T122,T124,T147
1	1	Covered	T123,T101,T122

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	30	0	0
SrcPulseCheck_M	17750577	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	30	0	0
T101	6376	1	0	0
T122	7391	2	0	0
T123	2600	1	0	0
T124	2697	2	0	0
T146	2603	2	0	0
T147	11916	3	0	0
T150	4054	1	0	0
T151	3820	1	0	0
T155	8140	1	0	0
T159	3415	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	17750577	30	0	0
T101	6602	1	0	0
T122	1597	2	0	0
T123	2217	1	0	0
T124	2486	2	0	0
T146	3265	2	0	0
T147	2399	3	0	0
T150	1581	1	0	0
T151	3683	1	0	0
T155	1816	1	0	0
T159	3200	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T98 T122 T125 

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T98,T122,T125
1	0	Covered	T98,T122,T125
1	1	Covered	T160,T156

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T98,T122,T125
1	0	Covered	T160,T156
1	1	Covered	T98,T122,T125

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	26	0	0
SrcPulseCheck_M	80538637	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	26	0	0
T98	6996	1	0	0
T122	7391	1	0	0
T124	2697	1	0	0
T125	8047	1	0	0
T126	7191	1	0	0
T144	9820	2	0	0
T146	2603	1	0	0
T148	5631	1	0	0
T152	3562	2	0	0
T159	3415	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	80538637	26	0	0
T98	14575	1	0	0
T122	7699	1	0	0
T124	11238	1	0	0
T125	8047	1	0	0
T126	7337	1	0	0
T144	10230	2	0	0
T146	14466	1	0	0
T148	5631	1	0	0
T152	14843	2	0	0
T159	14229	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T98 T123 T122 

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T98,T123,T122
1	0	Covered	T98,T123,T122
1	1	Covered	T144,T160,T154

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T98,T123,T122
1	0	Covered	T144,T160,T154
1	1	Covered	T98,T123,T122

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	28	0	0
SrcPulseCheck_M	80538637	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	28	0	0
T98	6996	1	0	0
T122	7391	1	0	0
T123	2600	1	0	0
T124	2697	1	0	0
T125	8047	1	0	0
T144	9820	3	0	0
T147	11916	1	0	0
T149	14742	1	0	0
T150	4054	1	0	0
T152	3562	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	80538637	28	0	0
T98	14575	1	0	0
T122	7699	1	0	0
T123	10002	1	0	0
T124	11238	1	0	0
T125	8047	1	0	0
T144	10230	3	0	0
T147	12037	1	0	0
T149	15197	1	0	0
T150	7509	1	0	0
T152	14843	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T95 T98 T123 

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T95,T98,T123
1	0	Covered	T95,T98,T123
1	1	Covered	T98,T156

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T95,T98,T123
1	0	Covered	T98,T156
1	1	Covered	T95,T98,T123

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	28	0	0
SrcPulseCheck_M	38644480	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	28	0	0
T95	3961	1	0	0
T98	6996	2	0	0
T101	6376	1	0	0
T123	2600	1	0	0
T125	8047	1	0	0
T146	2603	2	0	0
T147	11916	1	0	0
T149	14742	1	0	0
T152	3562	1	0	0
T161	2960	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	38644480	28	0	0
T95	7606	1	0	0
T98	6996	2	0	0
T101	13913	1	0	0
T123	4801	1	0	0
T125	3862	1	0	0
T146	6944	2	0	0
T147	5777	1	0	0
T149	7294	1	0	0
T152	7125	1	0	0
T161	5921	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T95 T121 T98 

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T95,T121,T98
1	0	Covered	T95,T121,T98
1	1	Covered	T98,T154,T162

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T95,T121,T98
1	0	Covered	T98,T154,T162
1	1	Covered	T95,T121,T98

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	35689686	27	0	0
SrcPulseCheck_M	38644480	27	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	27	0	0
T95	3961	1	0	0
T98	6996	2	0	0
T121	4014	1	0	0
T123	2600	1	0	0
T125	8047	1	0	0
T146	2603	1	0	0
T148	5631	1	0	0
T152	3562	1	0	0
T159	3415	1	0	0
T161	2960	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	38644480	27	0	0
T95	7606	1	0	0
T98	6996	2	0	0
T121	8028	1	0	0
T123	4801	1	0	0
T125	3862	1	0	0
T146	6944	1	0	0
T148	2703	1	0	0
T152	7125	1	0	0
T159	6830	1	0	0
T161	5921	1	0	0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T9 T40 

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T9,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	70722507	38886	0	0
SrcPulseCheck_M	1080170	38332	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722507	38886	0	0
T1	52692	60	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T40	0	40	0	0
T43	0	1	0	0
T51	0	47	0	0
T52	2367	0	0	0
T53	1445	0	0	0
T54	4976	0	0	0
T55	2430	0	0	0
T56	6826	0	0	0
T57	22618	0	0	0
T58	1551	0	0	0
T59	5711	0	0	0
T60	6180	0	0	0
T68	0	155	0	0
T69	0	80	0	0
T118	0	12	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080170	38332	0	0
T1	137	60	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T40	0	40	0	0
T43	0	1	0	0
T51	0	47	0	0
T52	172	0	0	0
T53	105	0	0	0
T54	362	0	0	0
T55	177	0	0	0
T56	497	0	0	0
T57	1649	0	0	0
T58	112	0	0	0
T59	416	0	0	0
T60	451	0	0	0
T68	0	155	0	0
T69	0	80	0	0
T118	0	12	0	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T9 T40 

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	34481633	38625	0	0
SrcPulseCheck_M	1080170	38073	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34481633	38625	0	0
T1	26313	60	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	38	0	0
T51	0	47	0	0
T52	1123	0	0	0
T53	710	0	0	0
T54	2476	0	0	0
T55	1189	0	0	0
T56	3353	0	0	0
T57	9177	0	0	0
T58	740	0	0	0
T59	3020	0	0	0
T60	3030	0	0	0
T68	0	155	0	0
T69	0	80	0	0
T118	0	12	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080170	38073	0	0
T1	137	60	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	38	0	0
T51	0	47	0	0
T52	172	0	0	0
T53	105	0	0	0
T54	362	0	0	0
T55	177	0	0	0
T56	497	0	0	0
T57	1649	0	0	0
T58	112	0	0	0
T59	416	0	0	0
T60	451	0	0	0
T68	0	155	0	0
T69	0	80	0	0
T118	0	12	0	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T9 T40 

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	17240419	38185	0	0
SrcPulseCheck_M	1080170	37637	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	38185	0	0
T1	13157	56	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	38	0	0
T51	0	47	0	0
T52	562	0	0	0
T53	354	0	0	0
T54	1238	0	0	0
T55	594	0	0	0
T56	1676	0	0	0
T57	4588	0	0	0
T58	370	0	0	0
T59	1510	0	0	0
T60	1515	0	0	0
T68	0	155	0	0
T69	0	80	0	0
T118	0	12	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1080170	37637	0	0
T1	137	56	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	38	0	0
T51	0	47	0	0
T52	172	0	0	0
T53	105	0	0	0
T54	362	0	0	0
T55	177	0	0	0
T56	497	0	0	0
T57	1649	0	0	0
T58	112	0	0	0
T59	416	0	0	0
T60	451	0	0	0
T68	0	155	0	0
T69	0	80	0	0
T118	0	12	0	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T9 T40 

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	78319349	46814	0	0
SrcPulseCheck_M	1081420	45879	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	46814	0	0
T1	66890	79	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	13	0	0
T51	0	95	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T54	5184	0	0	0
T55	2531	0	0	0
T56	7111	0	0	0
T57	23561	0	0	0
T58	1615	0	0	0
T59	5949	0	0	0
T60	6438	0	0	0
T68	0	215	0	0
T69	0	80	0	0
T118	0	12	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081420	45879	0	0
T1	161	79	0	0
T9	0	42	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	13	0	0
T51	0	95	0	0
T52	172	0	0	0
T53	105	0	0	0
T54	362	0	0	0
T55	177	0	0	0
T56	497	0	0	0
T57	1649	0	0	0
T58	112	0	0	0
T59	416	0	0	0
T60	451	0	0	0
T68	0	215	0	0
T69	0	80	0	0
T118	0	12	0	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
32         1/1                src_level <= 1'b0;
           Tests:       T4 T5 T6 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T4 T5 T6 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T4 T5 T6 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T4 T5 T6 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T4 T5 T6 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T9 T40 

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T9,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T9,T40
1	0	Covered	T1,T9,T40
1	1	Covered	T1,T9,T40

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	37579247	46092	0	0
SrcPulseCheck_M	1089201	46054	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37579247	46092	0	0
T1	32108	79	0	0
T9	0	39	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	36	0	0
T51	0	83	0	0
T52	1184	0	0	0
T53	722	0	0	0
T54	2489	0	0	0
T55	1215	0	0	0
T56	3413	0	0	0
T57	11310	0	0	0
T58	775	0	0	0
T59	2855	0	0	0
T60	3091	0	0	0
T68	0	215	0	0
T69	0	56	0	0
T118	0	12	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1089201	46054	0	0
T1	161	79	0	0
T9	0	39	0	0
T10	0	76	0	0
T11	0	50	0	0
T12	0	66	0	0
T40	0	36	0	0
T51	0	83	0	0
T52	172	0	0	0
T53	105	0	0	0
T54	362	0	0	0
T55	177	0	0	0
T56	497	0	0	0
T57	1649	0	0	0
T58	112	0	0	0
T59	416	0	0	0
T60	451	0	0	0
T68	0	215	0	0
T69	0	56	0	0
T118	0	12	0	0