Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	35689686	535790	0	0
clk_enables_rd_A	35689686	7448	0	0
clk_hints_rd_A	35689686	6801	0	0
extclk_ctrl_rd_A	35689686	10635	0	0
extclk_ctrl_regwen_rd_A	35689686	6091	0	0
jitter_enable_rd_A	35689686	14305	0	0
jitter_regwen_rd_A	35689686	5781	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	535790	0	0
T15	141917	7111	0	0
T16	19752	0	0	0
T17	131842	3398	0	0
T72	0	15382	0	0
T73	0	3358	0	0
T74	0	2099	0	0
T75	0	3010	0	0
T76	0	12727	0	0
T77	0	17335	0	0
T78	0	7741	0	0
T79	0	18327	0	0
T80	24407	0	0	0
T81	1544	0	0	0
T82	1733	0	0	0
T83	2337	0	0	0
T84	2163	0	0	0
T85	885	0	0	0
T86	2305	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	7448	0	0
T2	2223	0	0	0
T3	4971	0	0	0
T17	0	198	0	0
T55	2456	3	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0
T73	0	146	0	0
T74	0	79	0	0
T75	0	142	0	0
T87	2754	0	0	0
T88	0	3	0	0
T119	2255	0	0	0
T163	0	4	0	0
T164	0	22	0	0
T165	0	3	0	0
T166	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	6801	0	0
T2	2223	0	0	0
T3	4971	0	0	0
T17	0	124	0	0
T55	2456	3	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0
T73	0	152	0	0
T74	0	75	0	0
T87	2754	0	0	0
T88	0	3	0	0
T119	2255	0	0	0
T163	0	8	0	0
T164	0	13	0	0
T165	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	10635	0	0
T3	0	12	0	0
T5	2050	58	0	0
T6	1134	0	0	0
T22	0	3	0	0
T29	738	0	0	0
T30	1898	0	0	0
T31	959	0	0	0
T32	1766	10	0	0
T33	1179	0	0	0
T34	1057	0	0	0
T35	1578	0	0	0
T41	0	5	0	0
T70	1558	0	0	0
T87	0	79	0	0
T90	0	19	0	0
T119	0	16	0	0
T169	0	17	0	0
T170	0	10	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	6091	0	0
T3	4971	7	0	0
T17	0	153	0	0
T43	0	32	0	0
T73	0	108	0	0
T74	0	84	0	0
T88	1930	0	0	0
T89	15591	0	0	0
T90	1420	0	0	0
T91	1845	0	0	0
T92	1416	0	0	0
T93	2359	0	0	0
T94	1595	0	0	0
T130	2589	0	0	0
T171	0	34	0	0
T172	0	5	0	0
T173	0	69	0	0
T174	0	62	0	0
T175	0	29	0	0
T176	2296	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	14305	0	0
T2	2223	0	0	0
T3	4971	0	0	0
T17	0	742	0	0
T55	2456	85	0	0
T56	1777	0	0	0
T57	11545	0	0	0
T58	1615	0	0	0
T59	1606	0	0	0
T60	1222	0	0	0
T73	0	510	0	0
T87	2754	0	0	0
T88	0	132	0	0
T119	2255	0	0	0
T163	0	129	0	0
T164	0	428	0	0
T165	0	119	0	0
T167	0	66	0	0
T168	0	47	0	0
T177	0	43	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35689686	5781	0	0
T17	131842	137	0	0
T18	205536	0	0	0
T73	0	152	0	0
T74	0	108	0	0
T75	0	157	0	0
T78	0	186	0	0
T83	2337	0	0	0
T84	2163	0	0	0
T85	885	0	0	0
T86	2305	0	0	0
T178	0	867	0	0
T179	0	422	0	0
T180	0	125	0	0
T181	0	59	0	0
T182	0	189	0	0
T183	1372	0	0	0
T184	1624	0	0	0
T185	1536	0	0	0
T186	980	0	0	0