Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T6 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T5 T32 T33 

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T32,T34
1	1	Covered	T5,T32,T33

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	70722923	2793	0	0
g_div2.Div2Whole_A	70722923	3327	0	0
g_div4.Div4Stepped_A	34482014	2742	0	0
g_div4.Div4Whole_A	34482014	3148	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722923	2793	0	0
T5	4688	7	0	0
T6	2220	0	0	0
T29	2729	0	0	0
T30	7596	0	0	0
T31	1858	0	0	0
T32	1767	1	0	0
T33	2310	1	0	0
T34	6772	3	0	0
T35	1534	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	5	0	0
T70	1542	0	0	0
T71	0	11	0	0
T87	0	10	0	0
T119	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722923	3327	0	0
T5	4688	8	0	0
T6	2220	0	0	0
T29	2729	0	0	0
T30	7596	0	0	0
T31	1858	0	0	0
T32	1767	1	0	0
T33	2310	1	0	0
T34	6772	3	0	0
T35	1534	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	7	0	0
T70	1542	0	0	0
T71	0	10	0	0
T87	0	12	0	0
T119	0	11	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34482014	2742	0	0
T5	2695	7	0	0
T6	1098	0	0	0
T29	1353	0	0	0
T30	3786	0	0	0
T31	889	0	0	0
T32	880	1	0	0
T33	1136	1	0	0
T34	3667	3	0	0
T35	741	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	3	0	0
T70	725	0	0	0
T71	0	11	0	0
T87	0	10	0	0
T119	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34482014	3148	0	0
T5	2695	8	0	0
T6	1098	0	0	0
T29	1353	0	0	0
T30	3786	0	0	0
T31	889	0	0	0
T32	880	1	0	0
T33	1136	1	0	0
T34	3667	3	0	0
T35	741	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	7	0	0
T70	725	0	0	0
T71	0	10	0	0
T87	0	12	0	0
T119	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T6 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T5 T32 T33 

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T32,T34
1	1	Covered	T5,T32,T33

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	70722923	2793	0	0
g_div2.Div2Whole_A	70722923	3327	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722923	2793	0	0
T5	4688	7	0	0
T6	2220	0	0	0
T29	2729	0	0	0
T30	7596	0	0	0
T31	1858	0	0	0
T32	1767	1	0	0
T33	2310	1	0	0
T34	6772	3	0	0
T35	1534	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	5	0	0
T70	1542	0	0	0
T71	0	11	0	0
T87	0	10	0	0
T119	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722923	3327	0	0
T5	4688	8	0	0
T6	2220	0	0	0
T29	2729	0	0	0
T30	7596	0	0	0
T31	1858	0	0	0
T32	1767	1	0	0
T33	2310	1	0	0
T34	6772	3	0	0
T35	1534	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	7	0	0
T70	1542	0	0	0
T71	0	10	0	0
T87	0	12	0	0
T119	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T6 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T5 T32 T33 

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T32,T34
1	1	Covered	T5,T32,T33

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	34482014	2742	0	0
g_div4.Div4Whole_A	34482014	3148	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34482014	2742	0	0
T5	2695	7	0	0
T6	1098	0	0	0
T29	1353	0	0	0
T30	3786	0	0	0
T31	889	0	0	0
T32	880	1	0	0
T33	1136	1	0	0
T34	3667	3	0	0
T35	741	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	3	0	0
T70	725	0	0	0
T71	0	11	0	0
T87	0	10	0	0
T119	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34482014	3148	0	0
T5	2695	8	0	0
T6	1098	0	0	0
T29	1353	0	0	0
T30	3786	0	0	0
T31	889	0	0	0
T32	880	1	0	0
T33	1136	1	0	0
T34	3667	3	0	0
T35	741	0	0	0
T53	0	3	0	0
T58	0	2	0	0
T59	0	7	0	0
T70	725	0	0	0
T71	0	10	0	0
T87	0	12	0	0
T119	0	11	0	0