Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	104167203	387	0	0
StatusRise_A	104167203	387	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104167203	387	0	0
T1	38124	0	0	0
T31	2877	3	0	0
T32	5298	0	0	0
T33	3537	0	0	0
T34	3171	0	0	0
T35	4734	6	0	0
T49	0	4	0	0
T52	2295	0	0	0
T53	4335	0	0	0
T70	4674	0	0	0
T71	6006	0	0	0
T85	0	8	0	0
T92	0	6	0	0
T187	0	6	0	0
T188	0	9	0	0
T189	0	7	0	0
T190	0	3	0	0
T191	0	2	0	0
T192	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104167203	387	0	0
T1	38124	0	0	0
T31	2877	3	0	0
T32	5298	0	0	0
T33	3537	0	0	0
T34	3171	0	0	0
T35	4734	6	0	0
T49	0	4	0	0
T52	2295	0	0	0
T53	4335	0	0	0
T70	4674	0	0	0
T71	6006	0	0	0
T85	0	8	0	0
T92	0	6	0	0
T187	0	6	0	0
T188	0	9	0	0
T189	0	7	0	0
T190	0	3	0	0
T191	0	2	0	0
T192	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	34722401	127	0	0
StatusRise_A	34722401	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	127	0	0
T1	12708	0	0	0
T31	959	1	0	0
T32	1766	0	0	0
T33	1179	0	0	0
T34	1057	0	0	0
T35	1578	2	0	0
T49	0	2	0	0
T52	765	0	0	0
T53	1445	0	0	0
T70	1558	0	0	0
T71	2002	0	0	0
T85	0	2	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	127	0	0
T1	12708	0	0	0
T31	959	1	0	0
T32	1766	0	0	0
T33	1179	0	0	0
T34	1057	0	0	0
T35	1578	2	0	0
T49	0	2	0	0
T52	765	0	0	0
T53	1445	0	0	0
T70	1558	0	0	0
T71	2002	0	0	0
T85	0	2	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	34722401	123	0	0
StatusRise_A	34722401	123	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	123	0	0
T1	12708	0	0	0
T31	959	1	0	0
T32	1766	0	0	0
T33	1179	0	0	0
T34	1057	0	0	0
T35	1578	1	0	0
T49	0	1	0	0
T52	765	0	0	0
T53	1445	0	0	0
T70	1558	0	0	0
T71	2002	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	123	0	0
T1	12708	0	0	0
T31	959	1	0	0
T32	1766	0	0	0
T33	1179	0	0	0
T34	1057	0	0	0
T35	1578	1	0	0
T49	0	1	0	0
T52	765	0	0	0
T53	1445	0	0	0
T70	1558	0	0	0
T71	2002	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	34722401	137	0	0
StatusRise_A	34722401	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	137	0	0
T1	12708	0	0	0
T31	959	1	0	0
T32	1766	0	0	0
T33	1179	0	0	0
T34	1057	0	0	0
T35	1578	3	0	0
T49	0	1	0	0
T52	765	0	0	0
T53	1445	0	0	0
T70	1558	0	0	0
T71	2002	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	1	0	0
T192	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	137	0	0
T1	12708	0	0	0
T31	959	1	0	0
T32	1766	0	0	0
T33	1179	0	0	0
T34	1057	0	0	0
T35	1578	3	0	0
T49	0	1	0	0
T52	765	0	0	0
T53	1445	0	0	0
T70	1558	0	0	0
T71	2002	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	1	0	0
T192	0	5	0	0