Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	824444544	31605	0	0
CgEnOn_A	824444544	22924	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824444544	31605	0	0
T1	284364	0	0	0
T4	42248	7	0	0
T5	30603	3	0	0
T6	14229	8	0	0
T15	0	5	0	0
T29	17493	3	0	0
T30	48718	8	0	0
T31	20736	12	0	0
T32	19852	3	0	0
T33	25902	3	0	0
T34	77304	3	0	0
T35	17134	13	0	0
T49	0	5	0	0
T52	11292	0	0	0
T53	6951	0	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	8	0	0
T70	7335	0	0	0
T71	29703	0	0	0
T85	0	15	0	0
T92	0	12	0	0
T187	0	10	0	0
T188	0	15	0	0
T189	0	10	0	0
T190	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824444544	22924	0	0
T1	284364	0	0	0
T4	42248	4	0	0
T5	30603	0	0	0
T6	14229	5	0	0
T15	0	4	0	0
T24	0	3	0	0
T29	17493	0	0	0
T30	48718	5	0	0
T31	20736	9	0	0
T32	19852	0	0	0
T33	25902	0	0	0
T34	77304	0	0	0
T35	17134	10	0	0
T49	0	5	0	0
T52	11292	3	0	0
T53	6951	0	0	0
T54	0	6	0	0
T55	0	4	0	0
T56	0	8	0	0
T70	7335	0	0	0
T71	29703	0	0	0
T85	0	15	0	0
T88	0	4	0	0
T91	0	30	0	0
T92	0	18	0	0
T187	0	10	0	0
T188	0	15	0	0
T189	0	10	0	0
T190	0	5	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	34481633	141	0	0
CgEnOn_A	34481633	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34481633	141	0	0
T1	26313	0	0	0
T15	0	1	0	0
T31	889	1	0	0
T32	879	0	0	0
T33	1135	0	0	0
T34	3667	0	0	0
T35	741	1	0	0
T49	0	1	0	0
T52	1123	0	0	0
T53	710	0	0	0
T70	724	0	0	0
T71	4013	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34481633	141	0	0
T1	26313	0	0	0
T15	0	1	0	0
T31	889	1	0	0
T32	879	0	0	0
T33	1135	0	0	0
T34	3667	0	0	0
T35	741	1	0	0
T49	0	1	0	0
T52	1123	0	0	0
T53	710	0	0	0
T70	724	0	0	0
T71	4013	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17240419	141	0	0
CgEnOn_A	17240419	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	141	0	0
T1	13157	0	0	0
T15	0	1	0	0
T31	444	1	0	0
T32	439	0	0	0
T33	567	0	0	0
T34	1834	0	0	0
T35	370	1	0	0
T49	0	1	0	0
T52	562	0	0	0
T53	354	0	0	0
T70	362	0	0	0
T71	2006	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	141	0	0
T1	13157	0	0	0
T15	0	1	0	0
T31	444	1	0	0
T32	439	0	0	0
T33	567	0	0	0
T34	1834	0	0	0
T35	370	1	0	0
T49	0	1	0	0
T52	562	0	0	0
T53	354	0	0	0
T70	362	0	0	0
T71	2006	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17240419	141	0	0
CgEnOn_A	17240419	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	141	0	0
T1	13157	0	0	0
T15	0	1	0	0
T31	444	1	0	0
T32	439	0	0	0
T33	567	0	0	0
T34	1834	0	0	0
T35	370	1	0	0
T49	0	1	0	0
T52	562	0	0	0
T53	354	0	0	0
T70	362	0	0	0
T71	2006	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	141	0	0
T1	13157	0	0	0
T15	0	1	0	0
T31	444	1	0	0
T32	439	0	0	0
T33	567	0	0	0
T34	1834	0	0	0
T35	370	1	0	0
T49	0	1	0	0
T52	562	0	0	0
T53	354	0	0	0
T70	362	0	0	0
T71	2006	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17240419	141	0	0
CgEnOn_A	17240419	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	141	0	0
T1	13157	0	0	0
T15	0	1	0	0
T31	444	1	0	0
T32	439	0	0	0
T33	567	0	0	0
T34	1834	0	0	0
T35	370	1	0	0
T49	0	1	0	0
T52	562	0	0	0
T53	354	0	0	0
T70	362	0	0	0
T71	2006	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	141	0	0
T1	13157	0	0	0
T15	0	1	0	0
T31	444	1	0	0
T32	439	0	0	0
T33	567	0	0	0
T34	1834	0	0	0
T35	370	1	0	0
T49	0	1	0	0
T52	562	0	0	0
T53	354	0	0	0
T70	362	0	0	0
T71	2006	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	70722507	141	0	0
CgEnOn_A	70722507	126	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722507	141	0	0
T1	52692	0	0	0
T15	0	1	0	0
T31	1857	1	0	0
T32	1766	0	0	0
T33	2310	0	0	0
T34	6772	0	0	0
T35	1533	1	0	0
T49	0	1	0	0
T52	2367	0	0	0
T53	1445	0	0	0
T70	1542	0	0	0
T71	5490	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722507	126	0	0
T1	52692	0	0	0
T31	1857	1	0	0
T32	1766	0	0	0
T33	2310	0	0	0
T34	6772	0	0	0
T35	1533	1	0	0
T49	0	1	0	0
T52	2367	0	0	0
T53	1445	0	0	0
T70	1542	0	0	0
T71	5490	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78319349	134	0	0
CgEnOn_A	78319349	128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	134	0	0
T1	66890	0	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T49	0	2	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T70	1606	0	0	0
T71	5719	0	0	0
T85	0	2	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	128	0	0
T1	66890	0	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T49	0	2	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T70	1606	0	0	0
T71	5719	0	0	0
T85	0	2	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78319349	134	0	0
CgEnOn_A	78319349	128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	134	0	0
T1	66890	0	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T49	0	2	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T70	1606	0	0	0
T71	5719	0	0	0
T85	0	2	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	128	0	0
T1	66890	0	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T49	0	2	0	0
T52	2466	0	0	0
T53	1506	0	0	0
T70	1606	0	0	0
T71	5719	0	0	0
T85	0	2	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	37579247	138	0	0
CgEnOn_A	37579247	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37579247	138	0	0
T1	32108	0	0	0
T31	950	1	0	0
T32	883	0	0	0
T33	1154	0	0	0
T34	3386	0	0	0
T35	759	3	0	0
T49	0	1	0	0
T52	1184	0	0	0
T53	722	0	0	0
T70	771	0	0	0
T71	2744	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	1	0	0
T192	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37579247	137	0	0
T1	32108	0	0	0
T31	950	1	0	0
T32	883	0	0	0
T33	1154	0	0	0
T34	3386	0	0	0
T35	759	3	0	0
T49	0	1	0	0
T52	1184	0	0	0
T53	722	0	0	0
T70	771	0	0	0
T71	2744	0	0	0
T85	0	3	0	0
T92	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	1	0	0
T192	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T92
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17240419	5209	0	0
CgEnOn_A	17240419	3060	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	5209	0	0
T4	1640	2	0	0
T5	1345	1	0	0
T6	549	3	0	0
T29	676	1	0	0
T30	1893	1	0	0
T31	444	2	0	0
T32	439	1	0	0
T33	567	1	0	0
T34	1834	1	0	0
T35	370	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240419	3060	0	0
T4	1640	1	0	0
T5	1345	0	0	0
T6	549	2	0	0
T24	0	1	0	0
T29	676	0	0	0
T30	1893	0	0	0
T31	444	1	0	0
T32	439	0	0	0
T33	567	0	0	0
T34	1834	0	0	0
T35	370	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	10	0	0
T92	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T92
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	34481633	5228	0	0
CgEnOn_A	34481633	3079	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34481633	5228	0	0
T4	3281	2	0	0
T5	2695	1	0	0
T6	1098	2	0	0
T29	1352	1	0	0
T30	3785	1	0	0
T31	889	2	0	0
T32	879	1	0	0
T33	1135	1	0	0
T34	3667	1	0	0
T35	741	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34481633	3079	0	0
T4	3281	1	0	0
T5	2695	0	0	0
T6	1098	1	0	0
T24	0	1	0	0
T29	1352	0	0	0
T30	3785	0	0	0
T31	889	1	0	0
T32	879	0	0	0
T33	1135	0	0	0
T34	3667	0	0	0
T35	741	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	10	0	0
T92	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T92
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	70722507	5273	0	0
CgEnOn_A	70722507	3109	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722507	5273	0	0
T4	6586	2	0	0
T5	4687	1	0	0
T6	2220	3	0	0
T29	2729	1	0	0
T30	7595	1	0	0
T31	1857	2	0	0
T32	1766	1	0	0
T33	2310	1	0	0
T34	6772	1	0	0
T35	1533	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722507	3109	0	0
T4	6586	1	0	0
T5	4687	0	0	0
T6	2220	2	0	0
T24	0	1	0	0
T29	2729	0	0	0
T30	7595	0	0	0
T31	1857	1	0	0
T32	1766	0	0	0
T33	2310	0	0	0
T34	6772	0	0	0
T35	1533	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	10	0	0
T92	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T92
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	37579247	5267	0	0
CgEnOn_A	37579247	3100	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37579247	5267	0	0
T4	3293	2	0	0
T5	2344	1	0	0
T6	1110	3	0	0
T29	1364	1	0	0
T30	3797	1	0	0
T31	950	2	0	0
T32	883	1	0	0
T33	1154	1	0	0
T34	3386	1	0	0
T35	759	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37579247	3100	0	0
T4	3293	1	0	0
T5	2344	0	0	0
T6	1110	2	0	0
T24	0	1	0	0
T29	1364	0	0	0
T30	3797	0	0	0
T31	950	1	0	0
T32	883	0	0	0
T33	1154	0	0	0
T34	3386	0	0	0
T35	759	3	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	13	0	0
T92	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Covered	T4,T30,T54
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78319349	2351	0	0
CgEnOn_A	78319349	2345	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2351	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	0	0	0
T30	7912	5	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	8	0	0
T88	0	1	0	0
T92	0	2	0	0
T130	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2345	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	0	0	0
T30	7912	5	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	8	0	0
T88	0	1	0	0
T92	0	2	0	0
T130	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Covered	T4,T29,T30
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78319349	2390	0	0
CgEnOn_A	78319349	2384	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2390	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	1	0	0
T30	7912	3	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T92	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2384	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	1	0	0
T30	7912	3	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T92	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Covered	T4,T29,T30
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78319349	2389	0	0
CgEnOn_A	78319349	2383	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2389	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	1	0	0
T30	7912	4	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	9	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T92	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2383	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	1	0	0
T30	7912	4	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	9	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T92	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T35,T57
1	0	Covered	T4,T29,T30
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78319349	2387	0	0
CgEnOn_A	78319349	2381	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2387	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	1	0	0
T30	7912	3	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	7	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T92	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319349	2381	0	0
T4	6862	1	0	0
T5	4883	0	0	0
T6	2313	0	0	0
T29	2843	1	0	0
T30	7912	3	0	0
T31	1928	1	0	0
T32	1840	0	0	0
T33	2406	0	0	0
T34	7053	0	0	0
T35	1598	2	0	0
T54	0	7	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T92	0	2	0	0