Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	214512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

526153

1

T5

8

T6

11

T28

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	209407	1			T4	1		T6	16		T28	21
values[0x0]	251349	1			T4	2		T5	20		T6	15
values[0x1]	279909	1			T4	1		T5	17		T6	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147461	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

593204

1

T4

1

T5

13

T6

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2779	1			T144	5		T1	1		T54	2
valid_sources[0x01]	2780	1			T6	1		T28	2		T32	1
valid_sources[0x02]	3438	1			T54	1		T2	1		T166	1
valid_sources[0x03]	2294	1			T31	1		T82	1		T1	1
valid_sources[0x04]	3379	1			T1	2		T44	1		T60	3
valid_sources[0x05]	3203	1			T2	4		T99	2		T19	1
valid_sources[0x06]	2520	1			T30	1		T144	2		T50	1
valid_sources[0x07]	3488	1			T49	1		T53	1		T54	2
valid_sources[0x08]	2230	1			T129	1		T1	3		T51	1
valid_sources[0x09]	2716	1			T6	1		T31	1		T32	1
valid_sources[0x0a]	3567	1			T6	1		T33	8		T129	1
valid_sources[0x0b]	2558	1			T54	7		T3	1		T39	3
valid_sources[0x0c]	2349	1			T114	5		T54	13		T56	1
valid_sources[0x0d]	2910	1			T144	2		T1	1		T54	3
valid_sources[0x0e]	2900	1			T1	1		T51	2		T2	5
valid_sources[0x0f]	2814	1			T6	3		T31	3		T34	1
valid_sources[0x10]	2811	1			T6	1		T1	1		T58	1
valid_sources[0x11]	2234	1			T6	1		T34	3		T2	3
valid_sources[0x12]	3577	1			T144	9		T1	3		T213	1
valid_sources[0x13]	2937	1			T2	1		T10	3		T44	1
valid_sources[0x14]	3429	1			T130	2		T1	1		T2	1
valid_sources[0x15]	2110	1			T6	1		T28	2		T114	1
valid_sources[0x16]	2757	1			T33	13		T129	1		T130	1
valid_sources[0x17]	2403	1			T1	3		T54	3		T113	1
valid_sources[0x18]	2765	1			T31	1		T2	4		T166	1
valid_sources[0x19]	3273	1			T34	8		T53	2		T109	2
valid_sources[0x1a]	2586	1			T129	1		T54	2		T2	1
valid_sources[0x1b]	3487	1			T129	1		T2	2		T10	3
valid_sources[0x1c]	2421	1			T130	3		T1	2		T10	3
valid_sources[0x1d]	2125	1			T2	1		T173	2		T166	1
valid_sources[0x1e]	3403	1			T30	1		T54	2		T3	4
valid_sources[0x1f]	2563	1			T6	1		T32	2		T1	1
valid_sources[0x20]	2221	1			T28	4		T33	3		T34	1
valid_sources[0x21]	3252	1			T1	2		T54	3		T113	4
valid_sources[0x22]	2898	1			T1	1		T54	4		T2	5
valid_sources[0x23]	2356	1			T32	2		T1	1		T145	12
valid_sources[0x24]	3567	1			T2	2		T10	2		T173	1
valid_sources[0x25]	2614	1			T53	1		T54	1		T56	4
valid_sources[0x26]	3074	1			T143	1		T54	2		T58	5
valid_sources[0x27]	3499	1			T30	1		T31	5		T1	2
valid_sources[0x28]	2407	1			T56	3		T3	1		T10	1
valid_sources[0x29]	2894	1			T1	2		T54	2		T113	6
valid_sources[0x2a]	2743	1			T4	4		T50	1		T113	3
valid_sources[0x2b]	3416	1			T31	6		T2	2		T58	1
valid_sources[0x2c]	2485	1			T6	2		T1	1		T42	12
valid_sources[0x2d]	2629	1			T53	2		T54	2		T2	1
valid_sources[0x2e]	2945	1			T30	1		T1	1		T49	3
valid_sources[0x2f]	3475	1			T67	1		T82	2		T1	1
valid_sources[0x30]	2944	1			T1	2		T209	1		T44	2
valid_sources[0x31]	2532	1			T32	2		T1	2		T54	5
valid_sources[0x32]	2685	1			T33	3		T1	3		T51	1
valid_sources[0x33]	3043	1			T31	1		T129	1		T1	1
valid_sources[0x34]	2700	1			T33	3		T143	1		T1	1
valid_sources[0x35]	3467	1			T6	2		T31	4		T1	2
valid_sources[0x36]	4484	1			T1	1		T54	8		T44	1
valid_sources[0x37]	2796	1			T31	3		T34	7		T109	3
valid_sources[0x38]	2590	1			T28	1		T84	21		T142	7
valid_sources[0x39]	2989	1			T28	1		T31	1		T142	2
valid_sources[0x3a]	2669	1			T50	1		T51	1		T2	1
valid_sources[0x3b]	2355	1			T31	2		T32	1		T50	1
valid_sources[0x3c]	3190	1			T1	1		T43	10		T44	2
valid_sources[0x3d]	2568	1			T114	1		T130	2		T144	15
valid_sources[0x3e]	2421	1			T6	1		T28	2		T32	1
valid_sources[0x3f]	2685	1			T32	1		T51	1		T53	1
valid_sources[0x40]	2494	1			T31	3		T53	1		T10	3
valid_sources[0x41]	3301	1			T6	1		T32	2		T144	5
valid_sources[0x42]	2695	1			T143	1		T53	1		T54	7
valid_sources[0x43]	3153	1			T1	2		T2	1		T44	1
valid_sources[0x44]	2689	1			T6	1		T30	1		T144	6
valid_sources[0x45]	2197	1			T54	1		T2	4		T85	1
valid_sources[0x46]	3393	1			T28	2		T209	1		T2	2
valid_sources[0x47]	3190	1			T33	2		T34	4		T130	1
valid_sources[0x48]	2929	1			T114	1		T1	3		T51	1
valid_sources[0x49]	3039	1			T1	2		T51	1		T53	1
valid_sources[0x4a]	2526	1			T1	1		T54	2		T2	2
valid_sources[0x4b]	2400	1			T1	2		T2	1		T3	1
valid_sources[0x4c]	2737	1			T32	1		T143	1		T2	2
valid_sources[0x4d]	2823	1			T31	1		T2	1		T182	22
valid_sources[0x4e]	2891	1			T33	9		T54	2		T113	2
valid_sources[0x4f]	4047	1			T32	2		T53	1		T112	1
valid_sources[0x50]	2972	1			T33	2		T1	1		T50	2
valid_sources[0x51]	3061	1			T6	2		T142	2		T209	1
valid_sources[0x52]	2647	1			T142	2		T1	2		T109	4
valid_sources[0x53]	2131	1			T49	1		T54	1		T2	3
valid_sources[0x54]	2952	1			T31	2		T129	1		T1	2
valid_sources[0x55]	2905	1			T51	2		T54	2		T109	5
valid_sources[0x56]	2729	1			T54	1		T2	1		T3	2
valid_sources[0x57]	2691	1			T130	1		T1	1		T51	1
valid_sources[0x58]	2693	1			T6	1		T34	2		T53	1
valid_sources[0x59]	3157	1			T54	2		T2	2		T3	2
valid_sources[0x5a]	3187	1			T34	8		T1	1		T2	4
valid_sources[0x5b]	2747	1			T28	2		T1	1		T2	3
valid_sources[0x5c]	2907	1			T32	1		T142	1		T113	1
valid_sources[0x5d]	2863	1			T144	3		T1	1		T53	2
valid_sources[0x5e]	2619	1			T53	1		T54	2		T56	3
valid_sources[0x5f]	3630	1			T144	7		T54	2		T113	1
valid_sources[0x60]	2498	1			T6	1		T31	3		T1	1
valid_sources[0x61]	2532	1			T51	1		T53	1		T113	7
valid_sources[0x62]	2758	1			T82	2		T1	1		T10	2
valid_sources[0x63]	2990	1			T31	1		T1	1		T54	1
valid_sources[0x64]	2755	1			T1	1		T54	2		T2	1
valid_sources[0x65]	2683	1			T30	1		T1	1		T51	1
valid_sources[0x66]	2724	1			T1	1		T2	2		T27	22
valid_sources[0x67]	3052	1			T31	7		T34	2		T1	1
valid_sources[0x68]	2753	1			T33	3		T130	3		T1	1
valid_sources[0x69]	3028	1			T108	50		T53	1		T54	3
valid_sources[0x6a]	2918	1			T6	1		T32	1		T33	8
valid_sources[0x6b]	2607	1			T1	1		T2	2		T3	2
valid_sources[0x6c]	2741	1			T28	2		T54	2		T113	5
valid_sources[0x6d]	2437	1			T33	6		T1	3		T56	1
valid_sources[0x6e]	2518	1			T32	1		T129	1		T1	1
valid_sources[0x6f]	2968	1			T31	1		T1	1		T51	1
valid_sources[0x70]	3111	1			T31	4		T34	6		T1	2
valid_sources[0x71]	2286	1			T32	1		T2	1		T60	2
valid_sources[0x72]	2958	1			T1	3		T49	2		T10	2
valid_sources[0x73]	4955	1			T5	37		T31	1		T129	1
valid_sources[0x74]	2987	1			T33	13		T142	4		T1	1
valid_sources[0x75]	3126	1			T130	5		T1	1		T2	1
valid_sources[0x76]	3054	1			T130	1		T1	1		T54	5
valid_sources[0x77]	2586	1			T1	3		T51	1		T54	4
valid_sources[0x78]	3002	1			T31	1		T1	1		T2	1
valid_sources[0x79]	2690	1			T129	1		T1	2		T49	4
valid_sources[0x7a]	2981	1			T144	4		T53	1		T54	2
valid_sources[0x7b]	3308	1			T1	1		T53	1		T2	1
valid_sources[0x7c]	2919	1			T67	1		T1	1		T54	1
valid_sources[0x7d]	3327	1			T28	1		T130	2		T1	1
valid_sources[0x7e]	3040	1			T1	2		T53	3		T54	2
valid_sources[0x7f]	2885	1			T1	1		T2	1		T172	25
valid_sources[0x80]	2524	1			T22	2		T23	1		T85	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

144268

1

T6

7

T28

11

T30

3

values[0x0]

all_enables

biggest_size

204000

1

T5

7

T6

3

T28

2

values[0x1]

all_enables

biggest_size

177885

1

T5

1

T6

1

T28

2