Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T67
0	1	Covered	T5,T67,T52
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T34,T67
1	0	Covered	T110,T111,T41
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	204710131	8449	0	0
GateOpen_A	204710131	14668	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204710131	8449	0	0
T5	4556	44	0	0
T6	5253	0	0	0
T28	4691	0	0	0
T29	3314	0	0	0
T30	3336	0	0	0
T31	19637	0	0	0
T32	4710	0	0	0
T33	13440	0	0	0
T34	21421	4	0	0
T40	0	8	0	0
T52	0	33	0	0
T58	0	4	0	0
T67	3975	6	0	0
T83	0	4	0	0
T110	0	16	0	0
T111	0	13	0	0
T113	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204710131	14668	0	0
T5	4556	48	0	0
T6	5253	0	0	0
T28	4691	4	0	0
T29	3314	4	0	0
T30	3336	0	0	0
T31	19637	0	0	0
T32	4710	4	0	0
T33	13440	0	0	0
T34	21421	8	0	0
T67	3975	10	0	0
T83	0	8	0	0
T108	0	204	0	0
T110	0	20	0	0
T114	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T67
0	1	Covered	T5,T67,T52
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T34,T67
1	0	Covered	T110,T111,T41
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	22209486	2031	0	0
GateOpen_A	22209486	3580	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209486	2031	0	0
T5	491	11	0	0
T6	593	0	0	0
T28	563	0	0	0
T29	351	0	0	0
T30	378	0	0	0
T31	2160	0	0	0
T32	501	0	0	0
T33	1471	0	0	0
T34	2360	1	0	0
T40	0	2	0	0
T52	0	7	0	0
T58	0	1	0	0
T67	420	2	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	3	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209486	3580	0	0
T5	491	12	0	0
T6	593	0	0	0
T28	563	1	0	0
T29	351	1	0	0
T30	378	0	0	0
T31	2160	0	0	0
T32	501	1	0	0
T33	1471	0	0	0
T34	2360	2	0	0
T67	420	3	0	0
T83	0	2	0	0
T108	0	51	0	0
T110	0	5	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T67
0	1	Covered	T5,T67,T52
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T34,T67
1	0	Covered	T110,T111,T41
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	44419377	2130	0	0
GateOpen_A	44419377	3679	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44419377	2130	0	0
T5	981	10	0	0
T6	1188	0	0	0
T28	1125	0	0	0
T29	701	0	0	0
T30	757	0	0	0
T31	4319	0	0	0
T32	1002	0	0	0
T33	2942	0	0	0
T34	4720	1	0	0
T40	0	2	0	0
T52	0	8	0	0
T58	0	1	0	0
T67	839	1	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	3	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44419377	3679	0	0
T5	981	11	0	0
T6	1188	0	0	0
T28	1125	1	0	0
T29	701	1	0	0
T30	757	0	0	0
T31	4319	0	0	0
T32	1002	1	0	0
T33	2942	0	0	0
T34	4720	2	0	0
T67	839	2	0	0
T83	0	2	0	0
T108	0	51	0	0
T110	0	5	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T67
0	1	Covered	T5,T67,T52
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T34,T67
1	0	Covered	T110,T111,T41
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	90244366	2157	0	0
GateOpen_A	90244366	3716	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90244366	2157	0	0
T5	2056	12	0	0
T6	2315	0	0	0
T28	2002	0	0	0
T29	1508	0	0	0
T30	1467	0	0	0
T31	8772	0	0	0
T32	2138	0	0	0
T33	6018	0	0	0
T34	9560	1	0	0
T40	0	2	0	0
T52	0	10	0	0
T58	0	1	0	0
T67	1811	2	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	3	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90244366	3716	0	0
T5	2056	13	0	0
T6	2315	0	0	0
T28	2002	1	0	0
T29	1508	1	0	0
T30	1467	0	0	0
T31	8772	0	0	0
T32	2138	1	0	0
T33	6018	0	0	0
T34	9560	2	0	0
T67	1811	3	0	0
T83	0	2	0	0
T108	0	51	0	0
T110	0	5	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T67
0	1	Covered	T5,T67,T52
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T34,T67
1	0	Covered	T110,T111,T41
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	47836902	2131	0	0
GateOpen_A	47836902	3693	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47836902	2131	0	0
T5	1028	11	0	0
T6	1157	0	0	0
T28	1001	0	0	0
T29	754	0	0	0
T30	734	0	0	0
T31	4386	0	0	0
T32	1069	0	0	0
T33	3009	0	0	0
T34	4781	1	0	0
T40	0	2	0	0
T52	0	8	0	0
T58	0	1	0	0
T67	905	1	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	4	0	0
T113	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47836902	3693	0	0
T5	1028	12	0	0
T6	1157	0	0	0
T28	1001	1	0	0
T29	754	1	0	0
T30	734	0	0	0
T31	4386	0	0	0
T32	1069	1	0	0
T33	3009	0	0	0
T34	4781	2	0	0
T67	905	2	0	0
T83	0	2	0	0
T108	0	51	0	0
T110	0	5	0	0
T114	0	1	0	0