Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	198023995	33227	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198023995	33227	0	0
T7	274905	126	0	0
T8	0	198	0	0
T9	0	44	0	0
T11	0	312	0	0
T12	0	104	0	0
T13	0	152	0	0
T14	0	75	0	0
T15	0	233	0	0
T16	0	184	0	0
T17	0	411	0	0
T18	5645	0	0	0
T19	74020	0	0	0
T20	9120	0	0	0
T21	8475	0	0	0
T22	160775	0	0	0
T23	9505	0	0	0
T24	8335	0	0	0
T25	401960	0	0	0
T26	3765	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39604799	5046	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	5046	0	0
T7	54981	20	0	0
T8	0	32	0	0
T9	0	7	0	0
T11	0	40	0	0
T12	0	15	0	0
T13	0	25	0	0
T14	0	11	0	0
T15	0	37	0	0
T16	0	27	0	0
T17	0	55	0	0
T18	1129	0	0	0
T19	14804	0	0	0
T20	1824	0	0	0
T21	1695	0	0	0
T22	32155	0	0	0
T23	1901	0	0	0
T24	1667	0	0	0
T25	80392	0	0	0
T26	753	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39604799	4920	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	4920	0	0
T7	54981	20	0	0
T8	0	32	0	0
T9	0	7	0	0
T11	0	45	0	0
T12	0	15	0	0
T13	0	24	0	0
T14	0	11	0	0
T15	0	36	0	0
T16	0	23	0	0
T17	0	60	0	0
T18	1129	0	0	0
T19	14804	0	0	0
T20	1824	0	0	0
T21	1695	0	0	0
T22	32155	0	0	0
T23	1901	0	0	0
T24	1667	0	0	0
T25	80392	0	0	0
T26	753	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39604799	6690	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	6690	0	0
T7	54981	25	0	0
T8	0	40	0	0
T9	0	9	0	0
T11	0	61	0	0
T12	0	21	0	0
T13	0	31	0	0
T14	0	15	0	0
T15	0	47	0	0
T16	0	37	0	0
T17	0	80	0	0
T18	1129	0	0	0
T19	14804	0	0	0
T20	1824	0	0	0
T21	1695	0	0	0
T22	32155	0	0	0
T23	1901	0	0	0
T24	1667	0	0	0
T25	80392	0	0	0
T26	753	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39604799	6663	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	6663	0	0
T7	54981	25	0	0
T8	0	40	0	0
T9	0	9	0	0
T11	0	64	0	0
T12	0	20	0	0
T13	0	31	0	0
T14	0	15	0	0
T15	0	47	0	0
T16	0	37	0	0
T17	0	80	0	0
T18	1129	0	0	0
T19	14804	0	0	0
T20	1824	0	0	0
T21	1695	0	0	0
T22	32155	0	0	0
T23	1901	0	0	0
T24	1667	0	0	0
T25	80392	0	0	0
T26	753	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39604799	9908	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	9908	0	0
T7	54981	36	0	0
T8	0	54	0	0
T9	0	12	0	0
T11	0	102	0	0
T12	0	33	0	0
T13	0	41	0	0
T14	0	23	0	0
T15	0	66	0	0
T16	0	60	0	0
T17	0	136	0	0
T18	1129	0	0	0
T19	14804	0	0	0
T20	1824	0	0	0
T21	1695	0	0	0
T22	32155	0	0	0
T23	1901	0	0	0
T24	1667	0	0	0
T25	80392	0	0	0
T26	753	0	0	0