Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T108,T1,T54

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	39604799	37342585	0	0
AllClkBypReqTrue_A	39604799	81987	0	0
IoClkBypReqFalse_A	39604799	37285949	0	2397
IoClkBypReqTrue_A	39604799	134037	0	0
LcClkBypAckFalse_A	39604799	37347949	0	0
LcClkBypAckTrue_A	39604799	76623	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	37342585	0	0
T4	884	791	0	0
T5	2035	1900	0	0
T6	2314	2128	0	0
T28	2085	1897	0	0
T29	1524	1289	0	0
T30	1482	1245	0	0
T31	2102	2046	0	0
T32	2137	1946	0	0
T33	2381	2316	0	0
T34	1692	1646	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	81987	0	0
T6	2314	22	0	0
T28	2085	103	0	0
T29	1524	0	0	0
T30	1482	72	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T49	0	79	0	0
T51	0	209	0	0
T53	0	144	0	0
T67	943	0	0	0
T82	1338	47	0	0
T129	0	51	0	0
T130	0	268	0	0
T142	0	215	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	37285949	0	2397
T4	884	754	0	3
T5	2035	1898	0	3
T6	2314	1831	0	3
T28	2085	1776	0	3
T29	1524	1287	0	3
T30	1482	1315	0	3
T31	2102	2044	0	3
T32	2137	1944	0	3
T33	2381	2314	0	3
T34	1692	1644	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	134037	0	0
T4	884	35	0	0
T5	2035	0	0	0
T6	2314	317	0	0
T28	2085	222	0	0
T29	1524	0	0	0
T30	1482	0	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T49	0	276	0	0
T51	0	312	0	0
T53	0	315	0	0
T82	0	53	0	0
T130	0	541	0	0
T142	0	371	0	0
T143	0	67	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	37347949	0	0
T4	884	759	0	0
T5	2035	1900	0	0
T6	2314	2003	0	0
T28	2085	1884	0	0
T29	1524	1289	0	0
T30	1482	1317	0	0
T31	2102	2046	0	0
T32	2137	1946	0	0
T33	2381	2316	0	0
T34	1692	1646	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	76623	0	0
T4	884	32	0	0
T5	2035	0	0	0
T6	2314	147	0	0
T28	2085	116	0	0
T29	1524	0	0	0
T30	1482	0	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T49	0	102	0	0
T51	0	194	0	0
T53	0	213	0	0
T54	0	682	0	0
T130	0	329	0	0
T142	0	269	0	0
T143	0	2	0	0