Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	398951604	9459	0	0
TransStop_A	398951604	4969	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398951604	9459	0	0
T31	36548	21	0	0
T32	8908	0	0	0
T33	25072	34	0	0
T34	39836	4	0	0
T54	0	46	0	0
T58	0	4	0	0
T67	7548	0	0	0
T82	10920	0	0	0
T83	24936	4	0	0
T84	43236	7	0	0
T113	0	4	0	0
T114	8252	0	0	0
T129	9476	0	0	0
T144	0	32	0	0
T145	0	41	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398951604	4969	0	0
T31	36548	6	0	0
T32	8908	0	0	0
T33	25072	15	0	0
T34	39836	4	0	0
T54	0	28	0	0
T58	0	4	0	0
T67	7548	0	0	0
T82	10920	0	0	0
T83	24936	4	0	0
T84	43236	7	0	0
T113	0	4	0	0
T114	8252	0	0	0
T129	9476	0	0	0
T144	0	20	0	0
T145	0	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	99737901	2389	0	0
TransStop_A	99737901	1249	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	2389	0	0
T31	9137	6	0	0
T32	2227	0	0	0
T33	6268	9	0	0
T34	9959	1	0	0
T54	0	10	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	2	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	8	0	0
T145	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	1249	0	0
T31	9137	3	0	0
T32	2227	0	0	0
T33	6268	3	0	0
T34	9959	1	0	0
T54	0	6	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	2	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	5	0	0
T145	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	99737901	2351	0	0
TransStop_A	99737901	1259	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	2351	0	0
T31	9137	5	0	0
T32	2227	0	0	0
T33	6268	9	0	0
T34	9959	1	0	0
T54	0	12	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	1	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	8	0	0
T145	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	1259	0	0
T31	9137	1	0	0
T32	2227	0	0	0
T33	6268	5	0	0
T34	9959	1	0	0
T54	0	8	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	1	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	6	0	0
T145	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	99737901	2371	0	0
TransStop_A	99737901	1228	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	2371	0	0
T31	9137	4	0	0
T32	2227	0	0	0
T33	6268	9	0	0
T34	9959	1	0	0
T54	0	13	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	1	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	10	0	0
T145	0	14	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	1228	0	0
T31	9137	1	0	0
T32	2227	0	0	0
T33	6268	3	0	0
T34	9959	1	0	0
T54	0	7	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	1	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	6	0	0
T145	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	99737901	2348	0	0
TransStop_A	99737901	1233	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	2348	0	0
T31	9137	6	0	0
T32	2227	0	0	0
T33	6268	7	0	0
T34	9959	1	0	0
T54	0	11	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	3	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	6	0	0
T145	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737901	1233	0	0
T31	9137	1	0	0
T32	2227	0	0	0
T33	6268	4	0	0
T34	9959	1	0	0
T54	0	7	0	0
T58	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6234	1	0	0
T84	10809	3	0	0
T113	0	1	0	0
T114	2063	0	0	0
T129	2369	0	0	0
T144	0	3	0	0
T145	0	4	0	0