Unified Coverage Report :: Module :: clkmgr_meas_chk

Module : clkmgr_meas_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas	94.44	100.00	83.33			100.00
tb.dut.u_io_div2_meas	94.44	100.00	83.33			100.00
tb.dut.u_io_div4_meas	94.44	100.00	83.33			100.00
tb.dut.u_main_meas	94.44	100.00	83.33			100.00
tb.dut.u_usb_meas	94.44	100.00	83.33			100.00

---

Module Instance : tb.dut.u_io_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_io_div2_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_io_div4_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_main_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_usb_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

Line Coverage for Module : clkmgr_meas_chk

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

75                        always_comb begin
76         1/1              src_cfg_meas_en_valid_o = '0;
           Tests:       T4 T5 T6 
77         1/1              src_cfg_meas_en_o = src_cfg_meas_en_i;
           Tests:       T4 T5 T6 
78                      
79                          // if calibration is lost when measurement is currently enabled,
80                          // disable measurement enable.
81         1/1              if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
           Tests:       T4 T5 T6 
82                              prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83         1/1                src_cfg_meas_en_valid_o = 1'b1;
           Tests:       T7 T8 T9 
84         1/1                src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
           Tests:       T7 T8 T9 
85                          end
                        MISSING_ELSE
86                        end
87                      
88                        // A reqack module is used here instead of a pulse_saync
89                        // because the source pulses may toggle too fast for the
90                        // the destination to receive.
91                        logic src_err_req, src_err_ack;
92                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
93         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
94         1/1                src_err_req <= '0;
           Tests:       T4 T5 T6 
95         1/1              end else if (src_fast_err || src_slow_err) begin
           Tests:       T4 T5 T6 
96         1/1                src_err_req <= 1'b1;
           Tests:       T27 T45 T7 
97         1/1              end else if (src_err_req && src_err_ack) begin
           Tests:       T4 T5 T6 
98         1/1                src_err_req <= '0;
           Tests:       T27 T45 T7 
99                          end
                        MISSING_ELSE

---

Cond Coverage for Module : clkmgr_meas_chk

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T35,T9
1	0	Covered	T27,T45,T7

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T45,T7
1	1	Covered	T27,T45,T7

---

Branch Coverage for Module : clkmgr_meas_chk

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

81             if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
               -1-  
82                 prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83               src_cfg_meas_en_valid_o = 1'b1;
                 ==>
84               src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
85             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

93             if (!rst_src_ni) begin
               -1-  
94               src_err_req <= '0;
                 ==>
95             end else if (src_fast_err || src_slow_err) begin
                        -2-  
96               src_err_req <= 1'b1;
                 ==>
97             end else if (src_err_req && src_err_ack) begin
                        -3-  
98               src_err_req <= '0;
                 ==>
99             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T27,T45,T7
0	0	1	Covered	T27,T45,T7
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

75                        always_comb begin
76         1/1              src_cfg_meas_en_valid_o = '0;
           Tests:       T4 T5 T6 
77         1/1              src_cfg_meas_en_o = src_cfg_meas_en_i;
           Tests:       T4 T5 T6 
78                      
79                          // if calibration is lost when measurement is currently enabled,
80                          // disable measurement enable.
81         1/1              if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
           Tests:       T4 T5 T6 
82                              prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83         1/1                src_cfg_meas_en_valid_o = 1'b1;
           Tests:       T7 T8 T9 
84         1/1                src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
           Tests:       T7 T8 T9 
85                          end
                        MISSING_ELSE
86                        end
87                      
88                        // A reqack module is used here instead of a pulse_saync
89                        // because the source pulses may toggle too fast for the
90                        // the destination to receive.
91                        logic src_err_req, src_err_ack;
92                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
93         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
94         1/1                src_err_req <= '0;
           Tests:       T4 T5 T6 
95         1/1              end else if (src_fast_err || src_slow_err) begin
           Tests:       T4 T5 T6 
96         1/1                src_err_req <= 1'b1;
           Tests:       T45 T7 T35 
97         1/1              end else if (src_err_req && src_err_ack) begin
           Tests:       T4 T5 T6 
98         1/1                src_err_req <= '0;
           Tests:       T45 T7 T35 
99                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T13,T14
1	0	Covered	T45,T7,T35

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T7,T35
1	1	Covered	T45,T7,T35

---

Branch Coverage for Instance : tb.dut.u_io_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

81             if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
               -1-  
82                 prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83               src_cfg_meas_en_valid_o = 1'b1;
                 ==>
84               src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
85             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

93             if (!rst_src_ni) begin
               -1-  
94               src_err_req <= '0;
                 ==>
95             end else if (src_fast_err || src_slow_err) begin
                        -2-  
96               src_err_req <= 1'b1;
                 ==>
97             end else if (src_err_req && src_err_ack) begin
                        -3-  
98               src_err_req <= '0;
                 ==>
99             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T45,T7,T35
0	0	1	Covered	T45,T7,T35
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div2_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

75                        always_comb begin
76         1/1              src_cfg_meas_en_valid_o = '0;
           Tests:       T4 T5 T6 
77         1/1              src_cfg_meas_en_o = src_cfg_meas_en_i;
           Tests:       T4 T5 T6 
78                      
79                          // if calibration is lost when measurement is currently enabled,
80                          // disable measurement enable.
81         1/1              if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
           Tests:       T4 T5 T6 
82                              prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83         1/1                src_cfg_meas_en_valid_o = 1'b1;
           Tests:       T7 T8 T9 
84         1/1                src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
           Tests:       T7 T8 T9 
85                          end
                        MISSING_ELSE
86                        end
87                      
88                        // A reqack module is used here instead of a pulse_saync
89                        // because the source pulses may toggle too fast for the
90                        // the destination to receive.
91                        logic src_err_req, src_err_ack;
92                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
93         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
94         1/1                src_err_req <= '0;
           Tests:       T4 T5 T6 
95         1/1              end else if (src_fast_err || src_slow_err) begin
           Tests:       T4 T5 T6 
96         1/1                src_err_req <= 1'b1;
           Tests:       T27 T7 T35 
97         1/1              end else if (src_err_req && src_err_ack) begin
           Tests:       T4 T5 T6 
98         1/1                src_err_req <= '0;
           Tests:       T27 T7 T35 
99                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T9,T12
1	0	Covered	T27,T35,T9

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T7,T35
1	1	Covered	T27,T7,T35

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

81             if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
               -1-  
82                 prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83               src_cfg_meas_en_valid_o = 1'b1;
                 ==>
84               src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
85             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

93             if (!rst_src_ni) begin
               -1-  
94               src_err_req <= '0;
                 ==>
95             end else if (src_fast_err || src_slow_err) begin
                        -2-  
96               src_err_req <= 1'b1;
                 ==>
97             end else if (src_err_req && src_err_ack) begin
                        -3-  
98               src_err_req <= '0;
                 ==>
99             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T27,T7,T35
0	0	1	Covered	T27,T7,T35
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div4_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

75                        always_comb begin
76         1/1              src_cfg_meas_en_valid_o = '0;
           Tests:       T4 T5 T6 
77         1/1              src_cfg_meas_en_o = src_cfg_meas_en_i;
           Tests:       T4 T5 T6 
78                      
79                          // if calibration is lost when measurement is currently enabled,
80                          // disable measurement enable.
81         1/1              if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
           Tests:       T4 T5 T6 
82                              prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83         1/1                src_cfg_meas_en_valid_o = 1'b1;
           Tests:       T7 T8 T9 
84         1/1                src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
           Tests:       T7 T8 T9 
85                          end
                        MISSING_ELSE
86                        end
87                      
88                        // A reqack module is used here instead of a pulse_saync
89                        // because the source pulses may toggle too fast for the
90                        // the destination to receive.
91                        logic src_err_req, src_err_ack;
92                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
93         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
94         1/1                src_err_req <= '0;
           Tests:       T4 T5 T6 
95         1/1              end else if (src_fast_err || src_slow_err) begin
           Tests:       T4 T5 T6 
96         1/1                src_err_req <= 1'b1;
           Tests:       T7 T8 T35 
97         1/1              end else if (src_err_req && src_err_ack) begin
           Tests:       T4 T5 T6 
98         1/1                src_err_req <= '0;
           Tests:       T7 T8 T35 
99                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T35,T9,T46
1	0	Covered	T7,T8,T35

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T35
1	1	Covered	T7,T8,T35

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

81             if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
               -1-  
82                 prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83               src_cfg_meas_en_valid_o = 1'b1;
                 ==>
84               src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
85             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

93             if (!rst_src_ni) begin
               -1-  
94               src_err_req <= '0;
                 ==>
95             end else if (src_fast_err || src_slow_err) begin
                        -2-  
96               src_err_req <= 1'b1;
                 ==>
97             end else if (src_err_req && src_err_ack) begin
                        -3-  
98               src_err_req <= '0;
                 ==>
99             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T8,T35
0	0	1	Covered	T7,T8,T35
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_main_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

75                        always_comb begin
76         1/1              src_cfg_meas_en_valid_o = '0;
           Tests:       T4 T5 T6 
77         1/1              src_cfg_meas_en_o = src_cfg_meas_en_i;
           Tests:       T4 T5 T6 
78                      
79                          // if calibration is lost when measurement is currently enabled,
80                          // disable measurement enable.
81         1/1              if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
           Tests:       T4 T5 T6 
82                              prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83         1/1                src_cfg_meas_en_valid_o = 1'b1;
           Tests:       T7 T8 T9 
84         1/1                src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
           Tests:       T7 T8 T9 
85                          end
                        MISSING_ELSE
86                        end
87                      
88                        // A reqack module is used here instead of a pulse_saync
89                        // because the source pulses may toggle too fast for the
90                        // the destination to receive.
91                        logic src_err_req, src_err_ack;
92                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
93         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
94         1/1                src_err_req <= '0;
           Tests:       T4 T5 T6 
95         1/1              end else if (src_fast_err || src_slow_err) begin
           Tests:       T4 T5 T6 
96         1/1                src_err_req <= 1'b1;
           Tests:       T27 T7 T35 
97         1/1              end else if (src_err_req && src_err_ack) begin
           Tests:       T4 T5 T6 
98         1/1                src_err_req <= '0;
           Tests:       T27 T7 T35 
99                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T27,T7,T35
1	0	Covered	T7,T35,T9

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T7,T35
1	1	Covered	T27,T7,T35

---

Branch Coverage for Instance : tb.dut.u_main_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

81             if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
               -1-  
82                 prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83               src_cfg_meas_en_valid_o = 1'b1;
                 ==>
84               src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
85             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

93             if (!rst_src_ni) begin
               -1-  
94               src_err_req <= '0;
                 ==>
95             end else if (src_fast_err || src_slow_err) begin
                        -2-  
96               src_err_req <= 1'b1;
                 ==>
97             end else if (src_err_req && src_err_ack) begin
                        -3-  
98               src_err_req <= '0;
                 ==>
99             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T27,T7,T35
0	0	1	Covered	T27,T7,T35
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_usb_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

75                        always_comb begin
76         1/1              src_cfg_meas_en_valid_o = '0;
           Tests:       T4 T5 T6 
77         1/1              src_cfg_meas_en_o = src_cfg_meas_en_i;
           Tests:       T4 T5 T6 
78                      
79                          // if calibration is lost when measurement is currently enabled,
80                          // disable measurement enable.
81         1/1              if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
           Tests:       T4 T5 T6 
82                              prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83         1/1                src_cfg_meas_en_valid_o = 1'b1;
           Tests:       T7 T8 T9 
84         1/1                src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
           Tests:       T7 T8 T9 
85                          end
                        MISSING_ELSE
86                        end
87                      
88                        // A reqack module is used here instead of a pulse_saync
89                        // because the source pulses may toggle too fast for the
90                        // the destination to receive.
91                        logic src_err_req, src_err_ack;
92                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
93         1/1              if (!rst_src_ni) begin
           Tests:       T4 T5 T6 
94         1/1                src_err_req <= '0;
           Tests:       T4 T5 T6 
95         1/1              end else if (src_fast_err || src_slow_err) begin
           Tests:       T4 T5 T6 
96         1/1                src_err_req <= 1'b1;
           Tests:       T27 T7 T35 
97         1/1              end else if (src_err_req && src_err_ack) begin
           Tests:       T4 T5 T6 
98         1/1                src_err_req <= '0;
           Tests:       T27 T7 T35 
99                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T27,T9,T13
1	0	Covered	T27,T7,T35

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T7,T35
1	1	Covered	T27,T7,T35

---

Branch Coverage for Instance : tb.dut.u_usb_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

81             if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) &&
               -1-  
82                 prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin
83               src_cfg_meas_en_valid_o = 1'b1;
                 ==>
84               src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False;
85             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

93             if (!rst_src_ni) begin
               -1-  
94               src_err_req <= '0;
                 ==>
95             end else if (src_fast_err || src_slow_err) begin
                        -2-  
96               src_err_req <= 1'b1;
                 ==>
97             end else if (src_err_req && src_err_ack) begin
                        -3-  
98               src_err_req <= '0;
                 ==>
99             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T27,T7,T35
0	0	1	Covered	T27,T7,T35
0	0	0	Covered	T4,T5,T6