Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	40545146	575809	0	0
clk_enables_rd_A	40545146	8941	0	0
clk_hints_rd_A	40545146	8765	0	0
extclk_ctrl_rd_A	40545146	12620	0	0
extclk_ctrl_regwen_rd_A	40545146	7413	0	0
jitter_enable_rd_A	40545146	17978	0	0
jitter_regwen_rd_A	40545146	7258	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40545146	575809	0	0
T14	91584	4480	0	0
T15	42549	0	0	0
T16	191513	0	0	0
T17	196043	8911	0	0
T68	0	11308	0	0
T69	0	3783	0	0
T70	0	5357	0	0
T71	0	4074	0	0
T72	0	9662	0	0
T73	0	16142	0	0
T74	0	5724	0	0
T75	0	9313	0	0
T76	1359	0	0	0
T77	1544	0	0	0
T78	1298	0	0	0
T79	227310	0	0	0
T80	1684	0	0	0
T81	996	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40545146	8941	0	0
T34	1692	2	0	0
T58	0	2	0	0
T67	943	0	0	0
T71	0	237	0	0
T82	1338	0	0	0
T83	934	0	0	0
T84	1080	0	0	0
T110	1821	0	0	0
T113	0	1	0	0
T114	2000	0	0	0
T129	1681	0	0	0
T130	2544	0	0	0
T143	1114	0	0	0
T166	0	2	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	4	0	0
T170	0	17	0	0
T171	0	18	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40545146	8765	0	0
T34	1692	2	0	0
T58	0	2	0	0
T67	943	0	0	0
T71	0	168	0	0
T82	1338	0	0	0
T83	934	0	0	0
T84	1080	0	0	0
T110	1821	0	0	0
T113	0	4	0	0
T114	2000	0	0	0
T129	1681	0	0	0
T130	2544	0	0	0
T143	1114	0	0	0
T166	0	4	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	12	0	0
T171	0	17	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40545146	12620	0	0
T4	884	3	0	0
T5	2035	0	0	0
T6	2314	0	0	0
T10	0	42	0	0
T28	2085	0	0	0
T29	1524	0	0	0
T30	1482	13	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T129	0	5	0	0
T130	0	29	0	0
T172	0	19	0	0
T173	0	36	0	0
T174	0	47	0	0
T175	0	21	0	0
T176	0	61	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40545146	7413	0	0
T10	10140	25	0	0
T22	0	38	0	0
T37	2274	0	0	0
T38	2564	0	0	0
T39	6813	0	0	0
T40	652	0	0	0
T41	752	0	0	0
T42	2815	0	0	0
T43	2088	0	0	0
T44	32206	0	0	0
T71	0	177	0	0
T72	0	177	0	0
T87	0	34	0	0
T172	1838	0	0	0
T177	0	4	0	0
T178	0	28	0	0
T179	0	21	0	0
T180	0	59	0	0
T181	0	50	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40545146	17978	0	0
T34	1692	98	0	0
T58	0	113	0	0
T67	943	0	0	0
T82	1338	0	0	0
T83	934	0	0	0
T84	1080	0	0	0
T110	1821	0	0	0
T113	0	129	0	0
T114	2000	0	0	0
T129	1681	0	0	0
T130	2544	0	0	0
T143	1114	0	0	0
T166	0	80	0	0
T167	0	120	0	0
T168	0	105	0	0
T169	0	63	0	0
T170	0	490	0	0
T171	0	505	0	0
T182	0	67	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40545146	7258	0	0
T71	140801	155	0	0
T72	0	192	0	0
T74	0	132	0	0
T183	0	511	0	0
T184	0	500	0	0
T185	0	200	0	0
T186	0	376	0	0
T187	0	152	0	0
T188	0	543	0	0
T189	0	338	0	0
T190	35335	0	0	0
T191	920517	0	0	0
T192	753	0	0	0
T193	1369	0	0	0
T194	1744	0	0	0
T195	1429	0	0	0
T196	2897	0	0	0
T197	22209	0	0	0
T198	84930	0	0	0