Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	118814397	414	0	0
StatusRise_A	118814397	414	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118814397	414	0	0
T1	55956	0	0	0
T29	1524	1	0	0
T30	1482	0	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T41	0	6	0	0
T49	2914	0	0	0
T50	2222	0	0	0
T51	4632	0	0	0
T52	2518	0	0	0
T53	4468	0	0	0
T59	0	3	0	0
T67	943	0	0	0
T82	1338	0	0	0
T83	934	0	0	0
T84	1080	0	0	0
T108	38158	0	0	0
T110	3642	13	0	0
T111	0	10	0	0
T142	5008	0	0	0
T144	6532	0	0	0
T199	0	10	0	0
T200	0	9	0	0
T201	0	14	0	0
T202	0	5	0	0
T203	0	4	0	0
T204	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118814397	414	0	0
T1	55956	0	0	0
T29	1524	1	0	0
T30	1482	0	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T41	0	6	0	0
T49	2914	0	0	0
T50	2222	0	0	0
T51	4632	0	0	0
T52	2518	0	0	0
T53	4468	0	0	0
T59	0	3	0	0
T67	943	0	0	0
T82	1338	0	0	0
T83	934	0	0	0
T84	1080	0	0	0
T108	38158	0	0	0
T110	3642	13	0	0
T111	0	10	0	0
T142	5008	0	0	0
T144	6532	0	0	0
T199	0	10	0	0
T200	0	9	0	0
T201	0	14	0	0
T202	0	5	0	0
T203	0	4	0	0
T204	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39604799	136	0	0
StatusRise_A	39604799	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	136	0	0
T29	1524	1	0	0
T30	1482	0	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T41	0	2	0	0
T59	0	1	0	0
T67	943	0	0	0
T82	1338	0	0	0
T83	934	0	0	0
T84	1080	0	0	0
T110	0	5	0	0
T111	0	3	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	4	0	0
T202	0	2	0	0
T203	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	136	0	0
T29	1524	1	0	0
T30	1482	0	0	0
T31	2102	0	0	0
T32	2137	0	0	0
T33	2381	0	0	0
T34	1692	0	0	0
T41	0	2	0	0
T59	0	1	0	0
T67	943	0	0	0
T82	1338	0	0	0
T83	934	0	0	0
T84	1080	0	0	0
T110	0	5	0	0
T111	0	3	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	4	0	0
T202	0	2	0	0
T203	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39604799	145	0	0
StatusRise_A	39604799	145	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	145	0	0
T1	27978	0	0	0
T41	0	2	0	0
T49	1457	0	0	0
T50	1111	0	0	0
T51	2316	0	0	0
T52	1259	0	0	0
T53	2234	0	0	0
T59	0	1	0	0
T108	19079	0	0	0
T110	1821	4	0	0
T111	0	3	0	0
T142	2504	0	0	0
T144	3266	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	145	0	0
T1	27978	0	0	0
T41	0	2	0	0
T49	1457	0	0	0
T50	1111	0	0	0
T51	2316	0	0	0
T52	1259	0	0	0
T53	2234	0	0	0
T59	0	1	0	0
T108	19079	0	0	0
T110	1821	4	0	0
T111	0	3	0	0
T142	2504	0	0	0
T144	3266	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39604799	133	0	0
StatusRise_A	39604799	133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	133	0	0
T1	27978	0	0	0
T41	0	2	0	0
T49	1457	0	0	0
T50	1111	0	0	0
T51	2316	0	0	0
T52	1259	0	0	0
T53	2234	0	0	0
T59	0	1	0	0
T108	19079	0	0	0
T110	1821	4	0	0
T111	0	4	0	0
T142	2504	0	0	0
T144	3266	0	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39604799	133	0	0
T1	27978	0	0	0
T41	0	2	0	0
T49	1457	0	0	0
T50	1111	0	0	0
T51	2316	0	0	0
T52	1259	0	0	0
T53	2234	0	0	0
T59	0	1	0	0
T108	19079	0	0	0
T110	1821	4	0	0
T111	0	4	0	0
T142	2504	0	0	0
T144	3266	0	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0