Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T110,T108
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	1052259706	32894	0	0
CgEnOn_A	1052259706	23715	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052259706	32894	0	0
T1	50920	0	0	0
T4	2918	3	0	0
T5	3526	48	0	0
T6	4095	3	0	0
T28	3689	3	0	0
T29	4120	4	0	0
T30	4128	3	0	0
T31	24385	9	0	0
T32	5865	3	0	0
T33	16696	12	0	0
T34	26598	7	0	0
T41	0	10	0	0
T49	13625	0	0	0
T50	9476	0	0	0
T51	5539	0	0	0
T52	10803	0	0	0
T53	5334	0	0	0
T59	0	5	0	0
T67	1887	0	0	0
T83	0	1	0	0
T108	37220	0	0	0
T110	3615	25	0	0
T111	0	18	0	0
T142	5761	0	0	0
T144	14647	0	0	0
T199	0	15	0	0
T200	0	15	0	0
T201	0	25	0	0
T202	0	10	0	0
T203	0	10	0	0
T204	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052259706	23715	0	0
T1	50920	0	0	0
T5	3526	45	0	0
T6	4095	0	0	0
T28	3689	0	0	0
T29	4120	1	0	0
T30	4128	0	0	0
T31	24385	6	0	0
T32	5865	0	0	0
T33	16696	9	0	0
T34	26598	4	0	0
T41	0	10	0	0
T49	13625	0	0	0
T50	9476	0	0	0
T51	5539	0	0	0
T52	10803	35	0	0
T53	5334	0	0	0
T54	0	15	0	0
T58	0	3	0	0
T59	0	5	0	0
T67	4956	9	0	0
T82	2730	0	0	0
T83	0	4	0	0
T108	37220	0	0	0
T110	3615	37	0	0
T111	0	27	0	0
T113	0	3	0	0
T142	5761	0	0	0
T144	14647	0	0	0
T199	0	15	0	0
T200	0	15	0	0
T201	0	25	0	0
T202	0	10	0	0
T203	0	10	0	0
T204	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T108,T1
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	44418973	168	0	0
CgEnOn_A	44418973	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44418973	168	0	0
T1	8430	0	0	0
T41	0	2	0	0
T49	3117	0	0	0
T50	2082	0	0	0
T51	1291	0	0	0
T52	2386	0	0	0
T53	1243	0	0	0
T59	0	1	0	0
T108	7251	0	0	0
T110	779	4	0	0
T111	0	3	0	0
T142	1325	0	0	0
T144	3247	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44418973	168	0	0
T1	8430	0	0	0
T41	0	2	0	0
T49	3117	0	0	0
T50	2082	0	0	0
T51	1291	0	0	0
T52	2386	0	0	0
T53	1243	0	0	0
T59	0	1	0	0
T108	7251	0	0	0
T110	779	4	0	0
T111	0	3	0	0
T142	1325	0	0	0
T144	3247	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T108,T1
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	22209072	168	0	0
CgEnOn_A	22209072	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	168	0	0
T1	4216	0	0	0
T41	0	2	0	0
T49	1559	0	0	0
T50	1041	0	0	0
T51	644	0	0	0
T52	1193	0	0	0
T53	619	0	0	0
T59	0	1	0	0
T108	3630	0	0	0
T110	390	4	0	0
T111	0	3	0	0
T142	661	0	0	0
T144	1623	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	168	0	0
T1	4216	0	0	0
T41	0	2	0	0
T49	1559	0	0	0
T50	1041	0	0	0
T51	644	0	0	0
T52	1193	0	0	0
T53	619	0	0	0
T59	0	1	0	0
T108	3630	0	0	0
T110	390	4	0	0
T111	0	3	0	0
T142	661	0	0	0
T144	1623	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T108,T1
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	22209072	168	0	0
CgEnOn_A	22209072	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	168	0	0
T1	4216	0	0	0
T41	0	2	0	0
T49	1559	0	0	0
T50	1041	0	0	0
T51	644	0	0	0
T52	1193	0	0	0
T53	619	0	0	0
T59	0	1	0	0
T108	3630	0	0	0
T110	390	4	0	0
T111	0	3	0	0
T142	661	0	0	0
T144	1623	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	168	0	0
T1	4216	0	0	0
T41	0	2	0	0
T49	1559	0	0	0
T50	1041	0	0	0
T51	644	0	0	0
T52	1193	0	0	0
T53	619	0	0	0
T59	0	1	0	0
T108	3630	0	0	0
T110	390	4	0	0
T111	0	3	0	0
T142	661	0	0	0
T144	1623	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T108,T1
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	22209072	168	0	0
CgEnOn_A	22209072	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	168	0	0
T1	4216	0	0	0
T41	0	2	0	0
T49	1559	0	0	0
T50	1041	0	0	0
T51	644	0	0	0
T52	1193	0	0	0
T53	619	0	0	0
T59	0	1	0	0
T108	3630	0	0	0
T110	390	4	0	0
T111	0	3	0	0
T142	661	0	0	0
T144	1623	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	168	0	0
T1	4216	0	0	0
T41	0	2	0	0
T49	1559	0	0	0
T50	1041	0	0	0
T51	644	0	0	0
T52	1193	0	0	0
T53	619	0	0	0
T59	0	1	0	0
T108	3630	0	0	0
T110	390	4	0	0
T111	0	3	0	0
T142	661	0	0	0
T144	1623	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T108,T1
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90243933	168	0	0
CgEnOn_A	90243933	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90243933	168	0	0
T1	29842	0	0	0
T41	0	2	0	0
T49	5831	0	0	0
T50	4271	0	0	0
T51	2316	0	0	0
T52	4838	0	0	0
T53	2234	0	0	0
T59	0	1	0	0
T108	19079	0	0	0
T110	1666	4	0	0
T111	0	3	0	0
T142	2453	0	0	0
T144	6531	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90243933	152	0	0
T1	29842	0	0	0
T41	0	2	0	0
T49	5831	0	0	0
T50	4271	0	0	0
T51	2316	0	0	0
T52	4838	0	0	0
T53	2234	0	0	0
T59	0	1	0	0
T108	19079	0	0	0
T110	1666	4	0	0
T111	0	3	0	0
T142	2453	0	0	0
T144	6531	0	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	2	0	0
T203	0	2	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T110,T108
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99737448	143	0	0
CgEnOn_A	99737448	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	143	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	0	0	0
T32	2226	0	0	0
T33	6267	0	0	0
T34	9958	0	0	0
T41	0	2	0	0
T59	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	0	0	0
T84	10809	0	0	0
T110	0	5	0	0
T111	0	3	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	4	0	0
T202	0	2	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	137	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	0	0	0
T32	2226	0	0	0
T33	6267	0	0	0
T34	9958	0	0	0
T41	0	2	0	0
T59	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	0	0	0
T84	10809	0	0	0
T110	0	5	0	0
T111	0	3	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	4	0	0
T202	0	2	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T110,T108
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99737448	143	0	0
CgEnOn_A	99737448	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	143	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	0	0	0
T32	2226	0	0	0
T33	6267	0	0	0
T34	9958	0	0	0
T41	0	2	0	0
T59	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	0	0	0
T84	10809	0	0	0
T110	0	5	0	0
T111	0	3	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	4	0	0
T202	0	2	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	137	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	0	0	0
T32	2226	0	0	0
T33	6267	0	0	0
T34	9958	0	0	0
T41	0	2	0	0
T59	0	1	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	0	0	0
T84	10809	0	0	0
T110	0	5	0	0
T111	0	3	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	4	0	0
T202	0	2	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T108,T1
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47836459	141	0	0
CgEnOn_A	47836459	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47836459	141	0	0
T1	14921	0	0	0
T41	0	2	0	0
T49	2915	0	0	0
T50	2136	0	0	0
T51	1158	0	0	0
T52	2418	0	0	0
T53	1117	0	0	0
T59	0	1	0	0
T108	9540	0	0	0
T110	811	4	0	0
T111	0	4	0	0
T142	1226	0	0	0
T144	3266	0	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47836459	133	0	0
T1	14921	0	0	0
T41	0	2	0	0
T49	2915	0	0	0
T50	2136	0	0	0
T51	1158	0	0	0
T52	2418	0	0	0
T53	1117	0	0	0
T59	0	1	0	0
T108	9540	0	0	0
T110	811	4	0	0
T111	0	4	0	0
T142	1226	0	0	0
T144	3266	0	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	5	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T111,T41
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	22209072	5382	0	0
CgEnOn_A	22209072	3112	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	5382	0	0
T4	407	1	0	0
T5	490	16	0	0
T6	593	1	0	0
T28	562	1	0	0
T29	350	1	0	0
T30	377	1	0	0
T31	2159	1	0	0
T32	501	1	0	0
T33	1471	1	0	0
T34	2360	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22209072	3112	0	0
T5	490	15	0	0
T6	593	0	0	0
T28	562	0	0	0
T29	350	0	0	0
T30	377	0	0	0
T31	2159	0	0	0
T32	501	0	0	0
T33	1471	0	0	0
T34	2360	1	0	0
T52	0	10	0	0
T54	0	1	0	0
T58	0	1	0	0
T67	419	3	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	3	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T111,T41
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	44418973	5398	0	0
CgEnOn_A	44418973	3128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44418973	5398	0	0
T4	813	1	0	0
T5	981	16	0	0
T6	1188	1	0	0
T28	1125	1	0	0
T29	700	1	0	0
T30	756	1	0	0
T31	4318	1	0	0
T32	1001	1	0	0
T33	2941	1	0	0
T34	4720	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44418973	3128	0	0
T5	981	15	0	0
T6	1188	0	0	0
T28	1125	0	0	0
T29	700	0	0	0
T30	756	0	0	0
T31	4318	0	0	0
T32	1001	0	0	0
T33	2941	0	0	0
T34	4720	1	0	0
T52	0	12	0	0
T54	0	2	0	0
T58	0	1	0	0
T67	839	3	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	3	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T111,T41
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90243933	5414	0	0
CgEnOn_A	90243933	3128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90243933	5414	0	0
T4	1698	1	0	0
T5	2055	16	0	0
T6	2314	1	0	0
T28	2002	1	0	0
T29	1508	1	0	0
T30	1467	1	0	0
T31	8771	1	0	0
T32	2137	1	0	0
T33	6017	1	0	0
T34	9560	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90243933	3128	0	0
T5	2055	15	0	0
T6	2314	0	0	0
T28	2002	0	0	0
T29	1508	0	0	0
T30	1467	0	0	0
T31	8771	0	0	0
T32	2137	0	0	0
T33	6017	0	0	0
T34	9560	1	0	0
T52	0	13	0	0
T54	0	2	0	0
T58	0	1	0	0
T67	1811	3	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	3	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T110,T111,T41
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47836459	5402	0	0
CgEnOn_A	47836459	3109	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47836459	5402	0	0
T4	849	1	0	0
T5	1027	14	0	0
T6	1157	1	0	0
T28	1001	1	0	0
T29	753	1	0	0
T30	733	1	0	0
T31	4385	1	0	0
T32	1069	1	0	0
T33	3009	1	0	0
T34	4780	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47836459	3109	0	0
T5	1027	13	0	0
T6	1157	0	0	0
T28	1001	0	0	0
T29	753	0	0	0
T30	733	0	0	0
T31	4385	0	0	0
T32	1069	0	0	0
T33	3009	0	0	0
T34	4780	1	0	0
T52	0	11	0	0
T54	0	2	0	0
T58	0	1	0	0
T67	905	4	0	0
T83	0	1	0	0
T110	0	4	0	0
T111	0	4	0	0
T113	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T110,T108
1	0	Covered	T31,T33,T34
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99737448	2532	0	0
CgEnOn_A	99737448	2526	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2532	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	6	0	0
T32	2226	0	0	0
T33	6267	9	0	0
T34	9958	1	0	0
T54	0	10	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	2	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2526	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	6	0	0
T32	2226	0	0	0
T33	6267	9	0	0
T34	9958	1	0	0
T54	0	10	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	2	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T110,T108
1	0	Covered	T31,T33,T34
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99737448	2494	0	0
CgEnOn_A	99737448	2488	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2494	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	5	0	0
T32	2226	0	0	0
T33	6267	9	0	0
T34	9958	1	0	0
T54	0	12	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	1	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2488	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	5	0	0
T32	2226	0	0	0
T33	6267	9	0	0
T34	9958	1	0	0
T54	0	12	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	1	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T110,T108
1	0	Covered	T31,T33,T34
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99737448	2514	0	0
CgEnOn_A	99737448	2508	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2514	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	4	0	0
T32	2226	0	0	0
T33	6267	9	0	0
T34	9958	1	0	0
T54	0	13	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	1	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2508	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	4	0	0
T32	2226	0	0	0
T33	6267	9	0	0
T34	9958	1	0	0
T54	0	13	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	1	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T110,T108
1	0	Covered	T31,T33,T34
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99737448	2491	0	0
CgEnOn_A	99737448	2485	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2491	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	6	0	0
T32	2226	0	0	0
T33	6267	7	0	0
T34	9958	1	0	0
T54	0	11	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	3	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99737448	2485	0	0
T29	1562	1	0	0
T30	1528	0	0	0
T31	9137	6	0	0
T32	2226	0	0	0
T33	6267	7	0	0
T34	9958	1	0	0
T54	0	11	0	0
T67	1887	0	0	0
T82	2730	0	0	0
T83	6233	1	0	0
T84	10809	3	0	0
T110	0	5	0	0
T111	0	3	0	0
T144	0	6	0	0