Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 59439528 1 T4 2294 T5 3532 T6 2850
auto[1] 288152 1 T4 244 T30 936 T32 602


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 59391920 1 T4 2304 T5 3532 T6 2850
auto[1] 335760 1 T4 234 T28 456 T30 752


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 59361686 1 T4 2322 T5 3532 T6 2850
auto[1] 365994 1 T4 216 T28 526 T30 852


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 58669270 1 T4 242 T5 3532 T6 2850
auto[1] 1058410 1 T4 2296 T28 3828 T30 3200


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 43665758 1 T4 2322 T5 3492 T6 2850
auto[1] 16061922 1 T4 216 T5 40 T27 616


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 42615130 1 T4 170 T5 3492 T6 2850
auto[0] auto[0] auto[0] auto[0] auto[1] 15768324 1 T5 40 T27 616 T28 210
auto[0] auto[0] auto[0] auto[1] auto[0] 19676 1 T30 20 T32 58 T41 62
auto[0] auto[0] auto[0] auto[1] auto[1] 5916 1 T32 104 T41 94 T68 56
auto[0] auto[0] auto[1] auto[0] auto[0] 599738 1 T4 1924 T28 3364 T30 2146
auto[0] auto[0] auto[1] auto[0] auto[1] 211620 1 T4 84 T30 154 T32 80
auto[0] auto[0] auto[1] auto[1] auto[0] 33408 1 T4 12 T30 126 T32 40
auto[0] auto[0] auto[1] auto[1] auto[1] 8766 1 T4 32 T30 64 T32 12
auto[0] auto[1] auto[0] auto[0] auto[0] 59538 1 T28 52 T30 18 T32 30
auto[0] auto[1] auto[0] auto[0] auto[1] 922 1 T182 8 T24 2 T26 12
auto[0] auto[1] auto[0] auto[1] auto[0] 8888 1 T30 66 T32 72 T73 100
auto[0] auto[1] auto[0] auto[1] auto[1] 2342 1 T24 40 T26 42 T183 76
auto[0] auto[1] auto[1] auto[0] auto[0] 7538 1 T28 38 T30 54 T41 62
auto[0] auto[1] auto[1] auto[0] auto[1] 1726 1 T4 18 T32 6 T33 8
auto[0] auto[1] auto[1] auto[1] auto[0] 14846 1 T30 70 T41 276 T73 126
auto[0] auto[1] auto[1] auto[1] auto[1] 3308 1 T4 82 T32 74 T33 70
auto[1] auto[0] auto[0] auto[0] auto[0] 28058 1 T30 6 T32 44 T68 24
auto[1] auto[0] auto[0] auto[0] auto[1] 2844 1 T68 2 T127 2 T184 24
auto[1] auto[0] auto[0] auto[1] auto[0] 20672 1 T30 56 T68 94 T73 60
auto[1] auto[0] auto[0] auto[1] auto[1] 5746 1 T68 54 T127 38 T185 46
auto[1] auto[0] auto[1] auto[0] auto[0] 19508 1 T4 22 T28 160 T30 72
auto[1] auto[0] auto[1] auto[0] auto[1] 5140 1 T41 32 T43 10 T69 40
auto[1] auto[0] auto[1] auto[1] auto[0] 39582 1 T4 60 T30 174 T33 60
auto[1] auto[0] auto[1] auto[1] auto[1] 7792 1 T43 38 T20 62 T185 46
auto[1] auto[1] auto[0] auto[0] auto[0] 78736 1 T4 72 T28 38 T30 94
auto[1] auto[1] auto[0] auto[0] auto[1] 4808 1 T28 62 T68 22 T73 2
auto[1] auto[1] auto[0] auto[1] auto[0] 37372 1 T30 110 T32 158 T43 36
auto[1] auto[1] auto[0] auto[1] auto[1] 10298 1 T68 50 T73 46 T26 92
auto[1] auto[1] auto[1] auto[0] auto[0] 28038 1 T4 4 T28 266 T30 56
auto[1] auto[1] auto[1] auto[0] auto[1] 7860 1 T30 34 T33 34 T41 6
auto[1] auto[1] auto[1] auto[1] auto[0] 55030 1 T4 58 T30 120 T32 84
auto[1] auto[1] auto[1] auto[1] auto[1] 14510 1 T30 130 T41 82 T73 156

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