Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	195846	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

453784

1

T4

10

T6

4

T30

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	186821	1			T4	15		T30	42		T31	20
values[0x0]	220143	1			T4	16		T6	19		T30	18
values[0x1]	242666	1			T4	15		T6	12		T30	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	136159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

513471

1

T4

13

T6

6

T30

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2535	1			T54	2		T42	3		T13	7
valid_sources[0x01]	2258	1			T70	1		T1	7		T2	4
valid_sources[0x02]	2677	1			T109	1		T3	2		T47	1
valid_sources[0x03]	2120	1			T4	3		T98	5		T13	1
valid_sources[0x04]	2612	1			T30	1		T1	2		T3	1
valid_sources[0x05]	2178	1			T2	1		T40	1		T156	4
valid_sources[0x06]	2319	1			T4	1		T32	1		T54	1
valid_sources[0x07]	2305	1			T42	1		T3	1		T47	5
valid_sources[0x08]	2400	1			T54	1		T2	3		T3	4
valid_sources[0x09]	2323	1			T54	2		T109	1		T2	2
valid_sources[0x0a]	2305	1			T4	1		T2	3		T136	1
valid_sources[0x0b]	2095	1			T2	1		T47	2		T107	1
valid_sources[0x0c]	2445	1			T1	1		T13	2		T136	1
valid_sources[0x0d]	2460	1			T70	1		T109	1		T2	2
valid_sources[0x0e]	2309	1			T3	4		T29	1		T11	2
valid_sources[0x0f]	2015	1			T98	1		T1	2		T3	1
valid_sources[0x10]	2616	1			T109	2		T3	1		T138	1
valid_sources[0x11]	2729	1			T33	1		T54	1		T69	8
valid_sources[0x12]	2616	1			T107	1		T29	2		T11	7
valid_sources[0x13]	2664	1			T3	3		T40	1		T198	1
valid_sources[0x14]	2550	1			T33	1		T162	6		T107	1
valid_sources[0x15]	2461	1			T70	1		T109	1		T13	4
valid_sources[0x16]	2655	1			T30	1		T109	1		T3	4
valid_sources[0x17]	2202	1			T70	1		T109	2		T3	4
valid_sources[0x18]	2620	1			T109	1		T2	2		T3	1
valid_sources[0x19]	2044	1			T3	1		T13	12		T136	2
valid_sources[0x1a]	3693	1			T49	1		T3	2		T13	2
valid_sources[0x1b]	2440	1			T54	1		T3	1		T13	2
valid_sources[0x1c]	2647	1			T33	2		T110	35		T138	2
valid_sources[0x1d]	2250	1			T54	2		T98	1		T13	19
valid_sources[0x1e]	2817	1			T33	1		T2	1		T3	4
valid_sources[0x1f]	2232	1			T109	2		T1	3		T3	2
valid_sources[0x20]	2603	1			T54	1		T42	1		T136	1
valid_sources[0x21]	2466	1			T30	3		T36	1		T49	2
valid_sources[0x22]	2119	1			T49	9		T3	2		T13	8
valid_sources[0x23]	2298	1			T54	1		T29	2		T11	1
valid_sources[0x24]	2360	1			T109	1		T3	3		T138	3
valid_sources[0x25]	2566	1			T70	1		T2	1		T3	1
valid_sources[0x26]	1945	1			T3	3		T13	14		T29	1
valid_sources[0x27]	2776	1			T54	1		T1	2		T3	1
valid_sources[0x28]	2363	1			T4	4		T109	2		T187	52
valid_sources[0x29]	2247	1			T4	3		T33	1		T70	1
valid_sources[0x2a]	2442	1			T106	1		T3	1		T199	4
valid_sources[0x2b]	2446	1			T54	1		T109	1		T135	1
valid_sources[0x2c]	2385	1			T30	4		T31	4		T2	1
valid_sources[0x2d]	2111	1			T36	8		T54	2		T69	6
valid_sources[0x2e]	2323	1			T33	4		T54	1		T2	2
valid_sources[0x2f]	2156	1			T98	1		T109	1		T13	2
valid_sources[0x30]	2273	1			T3	5		T13	7		T107	1
valid_sources[0x31]	2080	1			T70	1		T2	1		T136	2
valid_sources[0x32]	4331	1			T30	1		T33	1		T98	1
valid_sources[0x33]	2773	1			T30	1		T109	1		T2	4
valid_sources[0x34]	2944	1			T1	2		T3	5		T13	23
valid_sources[0x35]	2743	1			T105	4		T2	2		T3	1
valid_sources[0x36]	2167	1			T109	1		T2	1		T3	1
valid_sources[0x37]	2575	1			T33	1		T2	1		T3	4
valid_sources[0x38]	3005	1			T54	1		T1	2		T2	1
valid_sources[0x39]	2862	1			T54	1		T13	16		T107	1
valid_sources[0x3a]	2406	1			T33	1		T109	1		T3	4
valid_sources[0x3b]	3003	1			T3	2		T27	1		T29	2
valid_sources[0x3c]	2261	1			T69	1		T2	1		T136	2
valid_sources[0x3d]	2496	1			T3	1		T13	1		T29	6
valid_sources[0x3e]	2236	1			T54	1		T29	1		T40	1
valid_sources[0x3f]	4329	1			T3	1		T29	5		T11	5
valid_sources[0x40]	2558	1			T4	1		T33	1		T70	1
valid_sources[0x41]	3146	1			T109	1		T3	2		T47	3
valid_sources[0x42]	2038	1			T31	5		T3	2		T136	1
valid_sources[0x43]	2250	1			T33	1		T13	8		T107	1
valid_sources[0x44]	2350	1			T54	1		T69	3		T42	2
valid_sources[0x45]	2657	1			T70	1		T13	6		T107	1
valid_sources[0x46]	2560	1			T4	1		T54	1		T70	1
valid_sources[0x47]	2800	1			T4	1		T3	1		T13	5
valid_sources[0x48]	2560	1			T109	1		T136	2		T107	1
valid_sources[0x49]	2727	1			T69	11		T109	1		T47	7
valid_sources[0x4a]	3269	1			T33	1		T109	1		T1	1
valid_sources[0x4b]	2477	1			T30	2		T54	2		T98	1
valid_sources[0x4c]	2981	1			T32	1		T54	2		T3	1
valid_sources[0x4d]	2440	1			T4	2		T70	1		T3	1
valid_sources[0x4e]	2285	1			T4	2		T2	3		T3	3
valid_sources[0x4f]	2585	1			T2	3		T42	3		T3	6
valid_sources[0x50]	2369	1			T30	1		T54	1		T3	2
valid_sources[0x51]	3044	1			T4	1		T30	1		T3	1
valid_sources[0x52]	2286	1			T54	4		T70	1		T3	3
valid_sources[0x53]	2853	1			T4	2		T109	2		T2	1
valid_sources[0x54]	3110	1			T98	2		T42	1		T3	3
valid_sources[0x55]	2245	1			T70	1		T109	1		T1	1
valid_sources[0x56]	2643	1			T30	3		T33	1		T109	1
valid_sources[0x57]	1991	1			T4	1		T106	1		T29	4
valid_sources[0x58]	2927	1			T1	1		T29	4		T74	1
valid_sources[0x59]	2420	1			T33	2		T2	2		T11	1
valid_sources[0x5a]	2196	1			T70	2		T2	6		T42	1
valid_sources[0x5b]	2212	1			T30	1		T32	1		T3	1
valid_sources[0x5c]	3562	1			T33	2		T69	7		T13	7
valid_sources[0x5d]	2370	1			T33	1		T109	1		T2	1
valid_sources[0x5e]	2776	1			T1	1		T3	1		T136	1
valid_sources[0x5f]	2560	1			T69	2		T1	6		T3	2
valid_sources[0x60]	1946	1			T109	1		T3	1		T29	1
valid_sources[0x61]	2232	1			T30	1		T3	1		T13	11
valid_sources[0x62]	3018	1			T54	1		T3	1		T28	3
valid_sources[0x63]	2088	1			T70	1		T109	1		T49	5
valid_sources[0x64]	2333	1			T1	1		T49	2		T3	2
valid_sources[0x65]	2943	1			T30	7		T2	4		T3	1
valid_sources[0x66]	2393	1			T30	4		T2	2		T3	1
valid_sources[0x67]	3084	1			T3	1		T13	6		T107	1
valid_sources[0x68]	2713	1			T54	2		T3	3		T136	1
valid_sources[0x69]	2226	1			T70	1		T49	2		T2	3
valid_sources[0x6a]	2458	1			T33	1		T54	1		T29	2
valid_sources[0x6b]	2535	1			T4	1		T13	13		T170	1
valid_sources[0x6c]	2465	1			T30	1		T70	1		T3	1
valid_sources[0x6d]	2740	1			T69	7		T3	2		T13	19
valid_sources[0x6e]	2690	1			T109	1		T2	2		T3	1
valid_sources[0x6f]	2137	1			T69	2		T3	1		T13	2
valid_sources[0x70]	2614	1			T54	1		T70	2		T3	2
valid_sources[0x71]	2366	1			T54	1		T111	2		T3	1
valid_sources[0x72]	2576	1			T30	5		T33	1		T36	1
valid_sources[0x73]	2953	1			T33	1		T70	1		T3	2
valid_sources[0x74]	2336	1			T3	2		T13	4		T136	1
valid_sources[0x75]	2529	1			T33	2		T3	1		T13	2
valid_sources[0x76]	2525	1			T33	1		T70	1		T109	1
valid_sources[0x77]	2532	1			T109	2		T1	4		T2	1
valid_sources[0x78]	2438	1			T13	4		T29	2		T198	1
valid_sources[0x79]	2528	1			T30	1		T3	3		T13	2
valid_sources[0x7a]	2189	1			T70	1		T3	2		T13	44
valid_sources[0x7b]	2254	1			T4	1		T33	1		T70	1
valid_sources[0x7c]	2095	1			T98	1		T109	1		T2	3
valid_sources[0x7d]	3506	1			T54	2		T3	1		T13	13
valid_sources[0x7e]	2263	1			T70	2		T13	15		T29	2
valid_sources[0x7f]	2466	1			T30	3		T69	1		T2	1
valid_sources[0x80]	2662	1			T109	1		T3	1		T13	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

126026

1

T4

7

T30

17

T31

11

values[0x0]

all_enables

biggest_size

176323

1

T4

2

T6

4

T30

8

values[0x1]

all_enables

biggest_size

151435

1

T4

1

T30

4

T31

2