Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T35
0	1	Covered	T6,T35,T44
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T35
1	0	Covered	T100,T46,T22
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	180234203	8326	0	0
GateOpen_A	180234203	14595	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180234203	8326	0	0
T6	3481	23	0	0
T22	0	3	0	0
T30	12141	4	0	0
T31	6412	0	0	0
T32	3337	0	0	0
T33	4787	0	0	0
T34	7214	0	0	0
T35	4147	18	0	0
T36	12650	0	0	0
T44	0	40	0	0
T46	0	15	0	0
T50	0	3	0	0
T54	3810	4	0	0
T69	15700	0	0	0
T100	0	13	0	0
T136	0	4	0	0
T162	0	20	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180234203	14595	0	0
T5	2481	4	0	0
T6	3481	27	0	0
T30	12141	8	0	0
T31	6412	4	0	0
T32	3337	4	0	0
T33	4787	4	0	0
T34	7214	4	0	0
T35	4147	18	0	0
T36	12650	4	0	0
T54	3810	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T35
0	1	Covered	T6,T35,T44
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T35
1	0	Covered	T100,T46,T22
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	19467684	1991	0	0
GateOpen_A	19467684	3555	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467684	1991	0	0
T6	369	5	0	0
T22	0	3	0	0
T30	1334	1	0	0
T31	704	0	0	0
T32	367	0	0	0
T33	514	0	0	0
T34	815	0	0	0
T35	450	4	0	0
T36	1388	0	0	0
T44	0	12	0	0
T46	0	4	0	0
T54	415	1	0	0
T69	1904	0	0	0
T100	0	3	0	0
T136	0	1	0	0
T162	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467684	3555	0	0
T5	258	1	0	0
T6	369	6	0	0
T30	1334	2	0	0
T31	704	1	0	0
T32	367	1	0	0
T33	514	1	0	0
T34	815	1	0	0
T35	450	4	0	0
T36	1388	1	0	0
T54	415	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T35
0	1	Covered	T6,T35,T44
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T35
1	0	Covered	T100,T46,T22
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	38935739	2109	0	0
GateOpen_A	38935739	3673	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38935739	2109	0	0
T6	738	6	0	0
T30	2667	1	0	0
T31	1408	0	0	0
T32	732	0	0	0
T33	1028	0	0	0
T34	1630	0	0	0
T35	900	5	0	0
T36	2776	0	0	0
T44	0	10	0	0
T46	0	4	0	0
T50	0	1	0	0
T54	830	1	0	0
T69	3812	0	0	0
T100	0	3	0	0
T136	0	1	0	0
T162	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38935739	3673	0	0
T5	516	1	0	0
T6	738	7	0	0
T30	2667	2	0	0
T31	1408	1	0	0
T32	732	1	0	0
T33	1028	1	0	0
T34	1630	1	0	0
T35	900	5	0	0
T36	2776	1	0	0
T54	830	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T35
0	1	Covered	T6,T35,T44
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T35
1	0	Covered	T100,T46,T22
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	79637029	2126	0	0
GateOpen_A	79637029	3695	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79637029	2126	0	0
T6	1583	5	0	0
T30	5427	1	0	0
T31	2867	0	0	0
T32	1492	0	0	0
T33	2163	0	0	0
T34	3179	0	0	0
T35	1865	5	0	0
T36	5657	0	0	0
T44	0	9	0	0
T46	0	4	0	0
T50	0	1	0	0
T54	1710	1	0	0
T69	6656	0	0	0
T100	0	3	0	0
T136	0	1	0	0
T162	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79637029	3695	0	0
T5	1138	1	0	0
T6	1583	6	0	0
T30	5427	2	0	0
T31	2867	1	0	0
T32	1492	1	0	0
T33	2163	1	0	0
T34	3179	1	0	0
T35	1865	5	0	0
T36	5657	1	0	0
T54	1710	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T35
0	1	Covered	T6,T35,T44
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T35
1	0	Covered	T100,T46,T22
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	42193751	2100	0	0
GateOpen_A	42193751	3672	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42193751	2100	0	0
T6	791	7	0	0
T30	2713	1	0	0
T31	1433	0	0	0
T32	746	0	0	0
T33	1082	0	0	0
T34	1590	0	0	0
T35	932	4	0	0
T36	2829	0	0	0
T44	0	9	0	0
T46	0	3	0	0
T50	0	1	0	0
T54	855	1	0	0
T69	3328	0	0	0
T100	0	4	0	0
T136	0	1	0	0
T162	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42193751	3672	0	0
T5	569	1	0	0
T6	791	8	0	0
T30	2713	2	0	0
T31	1433	1	0	0
T32	746	1	0	0
T33	1082	1	0	0
T34	1590	1	0	0
T35	932	4	0	0
T36	2829	1	0	0
T54	855	1	0	0