Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	178210935	27280	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178210935	27280	0	0
T10	111845	103	0	0
T11	0	299	0	0
T12	0	98	0	0
T14	0	171	0	0
T15	0	370	0	0
T16	0	299	0	0
T17	0	305	0	0
T18	0	39	0	0
T19	0	39	0	0
T20	0	644	0	0
T21	8970	0	0	0
T22	5620	0	0	0
T23	16905	0	0	0
T24	6965	0	0	0
T25	156830	0	0	0
T26	8830	0	0	0
T27	8220	0	0	0
T28	6605	0	0	0
T29	301670	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35642187	4123	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	4123	0	0
T10	22369	20	0	0
T11	0	48	0	0
T12	0	16	0	0
T14	0	26	0	0
T15	0	49	0	0
T16	0	57	0	0
T17	0	45	0	0
T18	0	6	0	0
T19	0	6	0	0
T20	0	102	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T27	1644	0	0	0
T28	1321	0	0	0
T29	60334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35642187	4135	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	4135	0	0
T10	22369	20	0	0
T11	0	48	0	0
T12	0	16	0	0
T14	0	26	0	0
T15	0	49	0	0
T16	0	57	0	0
T17	0	37	0	0
T18	0	6	0	0
T19	0	6	0	0
T20	0	103	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T27	1644	0	0	0
T28	1321	0	0	0
T29	60334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35642187	5466	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	5466	0	0
T10	22369	20	0	0
T11	0	60	0	0
T12	0	20	0	0
T14	0	34	0	0
T15	0	75	0	0
T16	0	57	0	0
T17	0	60	0	0
T18	0	8	0	0
T19	0	8	0	0
T20	0	132	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T27	1644	0	0	0
T28	1321	0	0	0
T29	60334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35642187	5451	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	5451	0	0
T10	22369	20	0	0
T11	0	60	0	0
T12	0	20	0	0
T14	0	34	0	0
T15	0	74	0	0
T16	0	57	0	0
T17	0	62	0	0
T18	0	8	0	0
T19	0	8	0	0
T20	0	127	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T27	1644	0	0	0
T28	1321	0	0	0
T29	60334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35642187	8105	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	8105	0	0
T10	22369	23	0	0
T11	0	83	0	0
T12	0	26	0	0
T14	0	51	0	0
T15	0	123	0	0
T16	0	71	0	0
T17	0	101	0	0
T18	0	11	0	0
T19	0	11	0	0
T20	0	180	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T27	1644	0	0	0
T28	1321	0	0	0
T29	60334	0	0	0