Unified Coverage Report :: Module

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	22344	22344	0	0
OutputsKnown_A	1553094771	1467771149	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	213853122	197669520	0	14364
gen_flops.gen_stable_chks.OutputDelay_A	503914293	475325849	0	16758
gen_flops.gen_stable_chks.OutputIfUnstable_A	503914293	129635	0	0
gen_no_flops.OutputDelay_A	835327356	794685972	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	22344	22344
T4	28	28
T5	28	28
T6	28	28
T30	28	28
T31	28	28
T32	28	28
T33	28	28
T34	28	28
T35	28	28
T36	28	28

OutputsKnown_A

Name	Attempts	Real Successes
Total	1553094771	1467771149
T4	65317	63005
T5	30766	25947
T6	42520	39060
T30	88200	85154
T31	57038	54215
T32	40124	36819
T33	57492	54067
T34	53615	51149
T35	36806	34865
T36	91124	88071

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	213853122	197669520	14364
T4	14892	14298	18
T5	7104	5898	18
T6	9696	8850	18
T30	8472	8118	18
T31	8952	8430	18
T32	9138	8298	18
T33	12972	12144	18
T34	5754	5424	18
T35	5712	5364	18
T36	8478	8136	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	503914293	475325849	16758
T4	17399	16704	21
T5	8205	6806	21
T6	11407	10415	21
T30	30858	29604	21
T31	17794	16767	21
T32	10749	9759	21
T33	15498	14508	21
T34	18340	17307	21
T35	11532	10846	21
T36	32055	30805	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	503914293	129635
T4	17399	145
T5	8205	10
T6	11407	53
T30	30858	16
T31	17794	48
T32	10749	19
T33	15498	107
T34	18340	34
T35	11532	25
T36	32055	12
T43	0	39
T69	0	147
T70	0	112
T71	0	84
T105	0	20
T106	0	24
T111	0	11
T112	0	92

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	835327356	794685972
T4	33026	31964
T5	15457	13204
T6	21417	19756
T30	48870	47393
T31	30292	28979
T32	20237	18723
T33	29022	27376
T34	29521	28379
T35	19562	18616
T36	50591	49091

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T32 T34  | T4 T32 T34  | T4 T32 T34  | T4 T32 T34 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T32 T34

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	79636599	75272701	0	0
gen_flops.gen_stable_chks.OutputDelay_A	79636599	75265849	0	2394
gen_flops.gen_stable_chks.OutputIfUnstable_A	79636599	18319	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	79636599	75272701
T4	2407	2313
T5	1137	947
T6	1583	1448
T30	5426	5209
T31	2866	2704
T32	1491	1356
T33	2162	2027
T34	3178	3002
T35	1864	1757
T36	5657	5440

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	79636599	75265849	2394
T4	2407	2310	3
T5	1137	944	3
T6	1583	1445	3
T30	5426	5206	3
T31	2866	2701	3
T32	1491	1353	3
T33	2162	2024	3
T34	3178	2999	3
T35	1864	1754	3
T36	5657	5437	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	79636599	18319
T4	2407	41
T5	1137	0
T6	1583	0
T30	5426	0
T31	2866	0
T32	1491	4
T33	2162	0
T34	3178	4
T35	1864	0
T36	5657	0
T69	0	76
T70	0	35
T71	0	37
T105	0	9
T106	0	11
T111	0	4
T112	0	48

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_no_flops.OutputDelay_A	35642187	32951853	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_no_flops.OutputDelay_A	35642187	32951853	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T32 T34  | T4 T32 T34  | T4 T32 T34  | T4 T32 T34 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T32 T34

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T32,T34

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T32,T34
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_stable_chks.OutputDelay_A	35642187	32944920	0	2394
gen_flops.gen_stable_chks.OutputIfUnstable_A	35642187	11178	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	35642187	11178
T4	2482	28
T5	1184	0
T6	1616	0
T30	1412	0
T31	1492	0
T32	1523	3
T33	2162	0
T34	959	4
T35	952	0
T36	1413	0
T43	0	22
T69	0	38
T70	0	33
T71	0	24
T106	0	5
T111	0	4
T112	0	30

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T34 T69  | T4 T34 T69  | T4 T34 T69  | T4 T34 T69 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T34 T69

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T34,T69

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T34,T69

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T34,T69

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T34,T69

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T34,T69
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T34,T69
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T34,T69
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T34,T69
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_stable_chks.OutputDelay_A	35642187	32944920	0	2394
gen_flops.gen_stable_chks.OutputIfUnstable_A	35642187	12500	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	35642187	12500
T4	2482	34
T5	1184	0
T6	1616	0
T30	1412	0
T31	1492	0
T32	1523	0
T33	2162	0
T34	959	2
T35	952	0
T36	1413	0
T43	0	17
T69	0	33
T70	0	44
T71	0	23
T105	0	11
T106	0	8
T111	0	3
T112	0	14

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	85871745	0	0
gen_no_flops.OutputDelay_A	88248330	85871745	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	85871745
T4	2507	2467
T5	1175	1063
T6	1648	1536
T30	5652	5555
T31	2986	2931
T32	1553	1499
T33	2253	2141
T34	3311	3271
T35	1941	1872
T36	5893	5781

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	88248330	85871745
T4	2507	2467
T5	1175	1063
T6	1648	1536
T30	5652	5555
T31	2986	2931
T32	1553	1499
T33	2253	2141
T34	3311	3271
T35	1941	1872
T36	5893	5781

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	79636599	77436891	0	0
gen_no_flops.OutputDelay_A	79636599	77436891	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	79636599	77436891
T4	2407	2368
T5	1137	1030
T6	1583	1475
T30	5426	5332
T31	2866	2814
T32	1491	1439
T33	2162	2055
T34	3178	3139
T35	1864	1798
T36	5657	5550

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	79636599	77436891
T4	2407	2368
T5	1137	1030
T6	1583	1475
T30	5426	5332
T31	2866	2814
T32	1491	1439
T33	2162	2055
T34	3178	3139
T35	1864	1798
T36	5657	5550

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	38935348	38935348	0	0
gen_no_flops.OutputDelay_A	38935348	38935348	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38935348	38935348
T4	1326	1326
T5	515	515
T6	738	738
T30	2666	2666
T31	1407	1407
T32	732	732
T33	1028	1028
T34	1630	1630
T35	899	899
T36	2775	2775

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38935348	38935348
T4	1326	1326
T5	515	515
T6	738	738
T30	2666	2666
T31	1407	1407
T32	732	732
T33	1028	1028
T34	1630	1630
T35	899	899
T36	2775	2775

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	19467275	19467275	0	0
gen_no_flops.OutputDelay_A	19467275	19467275	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	19467275	19467275
T4	663	663
T5	258	258
T6	369	369
T30	1333	1333
T31	704	704
T32	366	366
T33	514	514
T34	815	815
T35	450	450
T36	1388	1388

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	19467275	19467275
T4	663	663
T5	258	258
T6	369	369
T30	1333	1333
T31	704	704
T32	366	366
T33	514	514
T34	815	815
T35	450	450
T36	1388	1388

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	42193362	41065943	0	0
gen_no_flops.OutputDelay_A	42193362	41065943	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	42193362	41065943
T4	1203	1184
T5	568	514
T6	791	738
T30	2713	2667
T31	1433	1407
T32	745	719
T33	1081	1028
T34	1589	1570
T35	932	899
T36	2828	2775

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	42193362	41065943
T4	1203	1184
T5	568	514
T6	791	738
T30	2713	2667
T31	1433	1407
T32	745	719
T33	1081	1028
T34	1589	1570
T35	932	899
T36	2828	2775

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35642187	32944920	0	2394

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35642187	32944920	0	2394

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35642187	32944920	0	2394

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35642187	32944920	0	2394

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35642187	32944920	0	2394

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35642187	32944920	0	2394

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35642187	32944920	2394
T4	2482	2383	3
T5	1184	983	3
T6	1616	1475	3
T30	1412	1353	3
T31	1492	1405	3
T32	1523	1383	3
T33	2162	2024	3
T34	959	904	3
T35	952	894	3
T36	1413	1356	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_no_flops.OutputDelay_A	35642187	32951853	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_no_flops.OutputDelay_A	35642187	32951853	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_no_flops.OutputDelay_A	35642187	32951853	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	35642187	32951853	0	0
gen_no_flops.OutputDelay_A	35642187	32951853	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35642187	32951853
T4	2482	2386
T5	1184	986
T6	1616	1478
T30	1412	1356
T31	1492	1408
T32	1523	1386
T33	2162	2027
T34	959	907
T35	952	897
T36	1413	1359

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_flops.gen_stable_chks.OutputDelay_A	88248330	83542540	0	2394
gen_flops.gen_stable_chks.OutputIfUnstable_A	88248330	21969	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	88248330	83542540	2394
T4	2507	2407	3
T5	1175	974	3
T6	1648	1505	3
T30	5652	5423	3
T31	2986	2814	3
T32	1553	1410	3
T33	2253	2109	3
T34	3311	3125	3
T35	1941	1826	3
T36	5893	5664	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	88248330	21969
T4	2507	13
T5	1175	4
T6	1648	16
T30	5652	4
T31	2986	17
T32	1553	3
T33	2253	26
T34	3311	3
T35	1941	8
T36	5893	3

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_no_flops.OutputDelay_A	88248330	83549413	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_flops.gen_stable_chks.OutputDelay_A	88248330	83542540	0	2394
gen_flops.gen_stable_chks.OutputIfUnstable_A	88248330	22088	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	88248330	83542540	2394
T4	2507	2407	3
T5	1175	974	3
T6	1648	1505	3
T30	5652	5423	3
T31	2986	2814	3
T32	1553	1410	3
T33	2253	2109	3
T34	3311	3125	3
T35	1941	1826	3
T36	5893	5664	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	88248330	22088
T4	2507	11
T5	1175	4
T6	1648	11
T30	5652	4
T31	2986	13
T32	1553	3
T33	2253	25
T34	3311	5
T35	1941	5
T36	5893	3

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_no_flops.OutputDelay_A	88248330	83549413	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_flops.gen_stable_chks.OutputDelay_A	88248330	83542540	0	2394
gen_flops.gen_stable_chks.OutputIfUnstable_A	88248330	21755	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	88248330	83542540	2394
T4	2507	2407	3
T5	1175	974	3
T6	1648	1505	3
T30	5652	5423	3
T31	2986	2814	3
T32	1553	1410	3
T33	2253	2109	3
T34	3311	3125	3
T35	1941	1826	3
T36	5893	5664	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	88248330	21755
T4	2507	7
T5	1175	1
T6	1648	18
T30	5652	4
T31	2986	9
T32	1553	3
T33	2253	28
T34	3311	9
T35	1941	6
T36	5893	3

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_no_flops.OutputDelay_A	88248330	83549413	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_flops.gen_stable_chks.OutputDelay_A	88248330	83542540	0	2394
gen_flops.gen_stable_chks.OutputIfUnstable_A	88248330	21826	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	88248330	83542540	2394
T4	2507	2407	3
T5	1175	974	3
T6	1648	1505	3
T30	5652	5423	3
T31	2986	2814	3
T32	1553	1410	3
T33	2253	2109	3
T34	3311	3125	3
T35	1941	1826	3
T36	5893	5664	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	88248330	21826
T4	2507	11
T5	1175	1
T6	1648	8
T30	5652	4
T31	2986	9
T32	1553	3
T33	2253	28
T34	3311	7
T35	1941	6
T36	5893	3

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T6 T31 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T6 T31

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	798	798	0	0
OutputsKnown_A	88248330	83549413	0	0
gen_no_flops.OutputDelay_A	88248330	83549413	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	798	798
T4	1	1
T5	1	1
T6	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1
T36	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	88248330	83549413
T4	2507	2410
T5	1175	977
T6	1648	1508
T30	5652	5426
T31	2986	2817
T32	1553	1413
T33	2253	2112
T34	3311	3128
T35	1941	1829
T36	5893	5667

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl