Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T98,T99,T49

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	35642187	32866656	0	0
AllClkBypReqTrue_A	35642187	82913	0	0
IoClkBypReqFalse_A	35642187	32805912	0	2394
IoClkBypReqTrue_A	35642187	139089	0	0
LcClkBypAckFalse_A	35642187	32868761	0	0
LcClkBypAckTrue_A	35642187	80808	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	32866656	0	0
T4	2482	2138	0	0
T5	1184	985	0	0
T6	1616	1477	0	0
T30	1412	1355	0	0
T31	1492	1407	0	0
T32	1523	1385	0	0
T33	2162	2026	0	0
T34	959	906	0	0
T35	952	896	0	0
T36	1413	1358	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	82913	0	0
T4	2482	247	0	0
T5	1184	0	0	0
T6	1616	0	0	0
T30	1412	0	0	0
T31	1492	0	0	0
T32	1523	0	0	0
T33	2162	0	0	0
T34	959	0	0	0
T35	952	0	0	0
T36	1413	0	0	0
T43	0	95	0	0
T47	0	22	0	0
T69	0	295	0	0
T70	0	252	0	0
T71	0	97	0	0
T105	0	14	0	0
T106	0	102	0	0
T111	0	55	0	0
T135	0	10	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	32805912	0	2394
T4	2482	2026	0	3
T5	1184	983	0	3
T6	1616	1475	0	3
T30	1412	1353	0	3
T31	1492	1405	0	3
T32	1523	1354	0	3
T33	2162	2024	0	3
T34	959	866	0	3
T35	952	894	0	3
T36	1413	1356	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	139089	0	0
T4	2482	357	0	0
T5	1184	0	0	0
T6	1616	0	0	0
T30	1412	0	0	0
T31	1492	0	0	0
T32	1523	29	0	0
T33	2162	0	0	0
T34	959	38	0	0
T35	952	0	0	0
T36	1413	0	0	0
T43	0	280	0	0
T69	0	416	0	0
T70	0	274	0	0
T71	0	255	0	0
T106	0	94	0	0
T111	0	53	0	0
T112	0	271	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	32868761	0	0
T4	2482	2118	0	0
T5	1184	985	0	0
T6	1616	1477	0	0
T30	1412	1355	0	0
T31	1492	1407	0	0
T32	1523	1361	0	0
T33	2162	2026	0	0
T34	959	872	0	0
T35	952	896	0	0
T36	1413	1358	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	80808	0	0
T4	2482	267	0	0
T5	1184	0	0	0
T6	1616	0	0	0
T30	1412	0	0	0
T31	1492	0	0	0
T32	1523	24	0	0
T33	2162	0	0	0
T34	959	34	0	0
T35	952	0	0	0
T36	1413	0	0	0
T43	0	256	0	0
T69	0	267	0	0
T70	0	90	0	0
T71	0	164	0	0
T106	0	90	0	0
T111	0	49	0	0
T112	0	163	0	0