Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	352995068	9394	0	0
TransStop_A	352995068	4799	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352995068	9394	0	0
T21	0	2	0	0
T30	22612	4	0	0
T31	11948	10	0	0
T32	6216	0	0	0
T33	9016	16	0	0
T34	13248	0	0	0
T35	7768	0	0	0
T36	23572	0	0	0
T45	0	9	0	0
T48	0	19	0	0
T50	0	4	0	0
T54	7128	4	0	0
T69	27736	0	0	0
T100	8836	0	0	0
T109	0	26	0	0
T110	0	9	0	0
T136	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	352995068	4799	0	0
T21	0	3	0	0
T23	0	5	0	0
T30	22612	4	0	0
T31	11948	8	0	0
T32	6216	0	0	0
T33	9016	4	0	0
T34	13248	0	0	0
T35	7768	0	0	0
T36	23572	0	0	0
T45	0	4	0	0
T48	0	10	0	0
T50	0	4	0	0
T54	7128	4	0	0
T69	27736	0	0	0
T100	8836	0	0	0
T109	0	5	0	0
T110	0	9	0	0
T136	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	88248767	2341	0	0
TransStop_A	88248767	1171	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	2341	0	0
T30	5653	1	0	0
T31	2987	2	0	0
T32	1554	0	0	0
T33	2254	2	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T45	0	2	0	0
T48	0	3	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T109	0	7	0	0
T110	0	3	0	0
T136	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	1171	0	0
T23	0	5	0	0
T30	5653	1	0	0
T31	2987	2	0	0
T32	1554	0	0	0
T33	2254	1	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T109	0	2	0	0
T110	0	3	0	0
T136	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	88248767	2390	0	0
TransStop_A	88248767	1213	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	2390	0	0
T30	5653	1	0	0
T31	2987	3	0	0
T32	1554	0	0	0
T33	2254	4	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T45	0	3	0	0
T48	0	4	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T109	0	7	0	0
T110	0	1	0	0
T136	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	1213	0	0
T21	0	1	0	0
T30	5653	1	0	0
T31	2987	3	0	0
T32	1554	0	0	0
T33	2254	0	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T45	0	2	0	0
T48	0	2	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T136	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	88248767	2364	0	0
TransStop_A	88248767	1232	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	2364	0	0
T21	0	2	0	0
T30	5653	1	0	0
T31	2987	2	0	0
T32	1554	0	0	0
T33	2254	6	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T48	0	6	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T109	0	6	0	0
T110	0	2	0	0
T136	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	1232	0	0
T21	0	1	0	0
T30	5653	1	0	0
T31	2987	1	0	0
T32	1554	0	0	0
T33	2254	2	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T48	0	4	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T109	0	1	0	0
T110	0	2	0	0
T136	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	88248767	2299	0	0
TransStop_A	88248767	1183	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	2299	0	0
T30	5653	1	0	0
T31	2987	3	0	0
T32	1554	0	0	0
T33	2254	4	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T45	0	4	0	0
T48	0	6	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T109	0	6	0	0
T110	0	3	0	0
T136	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248767	1183	0	0
T21	0	1	0	0
T30	5653	1	0	0
T31	2987	2	0	0
T32	1554	0	0	0
T33	2254	1	0	0
T34	3312	0	0	0
T35	1942	0	0	0
T36	5893	0	0	0
T45	0	2	0	0
T48	0	3	0	0
T50	0	1	0	0
T54	1782	1	0	0
T69	6934	0	0	0
T100	2209	0	0	0
T110	0	3	0	0
T136	0	1	0	0