SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_lost_calib_regwen_sva_if | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
RegwenOff_A | 35642187 | 2427661 | 0 | 57 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 35642187 | 2427661 | 0 | 57 |
T2 | 16761 | 799 | 0 | 1 |
T3 | 24792 | 0 | 0 | 0 |
T10 | 0 | 4130 | 0 | 1 |
T11 | 0 | 18718 | 0 | 1 |
T12 | 0 | 6887 | 0 | 1 |
T13 | 39212 | 0 | 0 | 0 |
T14 | 0 | 13862 | 0 | 0 |
T15 | 0 | 39243 | 0 | 1 |
T16 | 0 | 11174 | 0 | 1 |
T17 | 0 | 27286 | 0 | 0 |
T18 | 0 | 4645 | 0 | 0 |
T19 | 0 | 0 | 0 | 1 |
T37 | 0 | 1311 | 0 | 1 |
T41 | 0 | 0 | 0 | 1 |
T42 | 1956 | 0 | 0 | 0 |
T43 | 2175 | 0 | 0 | 0 |
T44 | 1508 | 0 | 0 | 0 |
T45 | 1876 | 0 | 0 | 0 |
T46 | 1399 | 0 | 0 | 0 |
T47 | 2476 | 0 | 0 | 0 |
T48 | 1763 | 0 | 0 | 0 |
T137 | 0 | 0 | 0 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |