Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	35642187	2427661	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	2427661	0	57
T2	16761	799	0	1
T3	24792	0	0	0
T10	0	4130	0	1
T11	0	18718	0	1
T12	0	6887	0	1
T13	39212	0	0	0
T14	0	13862	0	0
T15	0	39243	0	1
T16	0	11174	0	1
T17	0	27286	0	0
T18	0	4645	0	0
T19	0	0	0	1
T37	0	1311	0	1
T41	0	0	0	1
T42	1956	0	0	0
T43	2175	0	0	0
T44	1508	0	0	0
T45	1876	0	0	0
T46	1399	0	0	0
T47	2476	0	0	0
T48	1763	0	0	0
T137	0	0	0	1