Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	36456208	489304	0	0
clk_enables_rd_A	36456208	8913	0	0
clk_hints_rd_A	36456208	8202	0	0
extclk_ctrl_rd_A	36456208	11853	0	0
extclk_ctrl_regwen_rd_A	36456208	6707	0	0
jitter_enable_rd_A	36456208	16258	0	0
jitter_regwen_rd_A	36456208	6986	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36456208	489304	0	0
T17	215619	5577	0	0
T18	136043	4825	0	0
T19	54283	0	0	0
T20	178939	0	0	0
T55	0	8060	0	0
T56	0	10091	0	0
T57	0	14266	0	0
T58	0	9950	0	0
T59	0	10755	0	0
T60	0	10246	0	0
T61	0	2065	0	0
T62	0	7253	0	0
T63	1151	0	0	0
T64	1449	0	0	0
T65	1178	0	0	0
T66	1633	0	0	0
T67	1515	0	0	0
T68	2435	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36456208	8913	0	0
T10	22369	0	0	0
T17	0	259	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T57	0	273	0	0
T66	0	4	0	0
T107	15665	0	0	0
T136	1918	4	0	0
T156	0	9	0	0
T157	0	5	0	0
T158	0	6	0	0
T159	0	11	0	0
T160	0	2	0	0
T161	0	4	0	0
T162	1198	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36456208	8202	0	0
T10	22369	0	0	0
T17	0	192	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T57	0	337	0	0
T58	0	250	0	0
T61	0	144	0	0
T66	0	3	0	0
T107	15665	0	0	0
T136	1918	3	0	0
T156	0	1	0	0
T158	0	4	0	0
T159	0	13	0	0
T161	0	11	0	0
T162	1198	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36456208	11853	0	0
T13	0	141	0	0
T26	0	23	0	0
T34	959	12	0	0
T35	952	0	0	0
T36	1413	0	0	0
T54	1692	0	0	0
T69	2010	0	0	0
T70	1703	0	0	0
T71	1515	0	0	0
T75	0	25	0	0
T76	0	34	0	0
T89	0	26	0	0
T98	8268	0	0	0
T100	1263	0	0	0
T109	1862	0	0	0
T111	0	10	0	0
T139	0	64	0	0
T163	0	15	0	0
T164	0	26	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36456208	6707	0	0
T13	39212	61	0	0
T17	0	205	0	0
T39	60196	0	0	0
T57	0	313	0	0
T58	0	286	0	0
T61	0	111	0	0
T101	1148	0	0	0
T107	15665	0	0	0
T135	720	0	0	0
T136	1918	0	0	0
T138	1915	0	0	0
T139	2117	0	0	0
T162	1198	0	0	0
T165	0	18	0	0
T166	0	11	0	0
T167	0	39	0	0
T168	0	18	0	0
T169	0	102	0	0
T170	1016	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36456208	16258	0	0
T10	22369	0	0	0
T17	0	214	0	0
T21	1794	0	0	0
T22	1124	0	0	0
T23	3381	0	0	0
T24	1393	0	0	0
T25	31366	0	0	0
T26	1766	0	0	0
T57	0	757	0	0
T66	0	100	0	0
T107	15665	0	0	0
T136	1918	108	0	0
T156	0	92	0	0
T157	0	74	0	0
T158	0	112	0	0
T159	0	343	0	0
T160	0	90	0	0
T162	1198	0	0	0
T171	0	48	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36456208	6986	0	0
T17	215619	262	0	0
T18	136043	0	0	0
T19	54283	0	0	0
T20	178939	0	0	0
T57	0	288	0	0
T58	0	239	0	0
T61	0	121	0	0
T63	1151	0	0	0
T64	1449	0	0	0
T65	1178	0	0	0
T66	1633	0	0	0
T67	1515	0	0	0
T68	2435	0	0	0
T169	0	209	0	0
T172	0	311	0	0
T173	0	482	0	0
T174	0	158	0	0
T175	0	129	0	0
T176	0	292	0	0