Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	106926561	413	0	0
StatusRise_A	106926561	413	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106926561	413	0	0
T5	1184	1	0	0
T6	1616	0	0	0
T22	0	9	0	0
T30	1412	0	0	0
T31	1492	0	0	0
T32	1523	0	0	0
T33	2162	0	0	0
T34	959	0	0	0
T35	952	0	0	0
T36	1413	0	0	0
T46	0	11	0	0
T54	1692	0	0	0
T67	0	14	0	0
T70	3406	0	0	0
T71	3030	0	0	0
T88	0	6	0	0
T98	16536	0	0	0
T100	2526	13	0	0
T105	2228	0	0	0
T106	2694	0	0	0
T109	3724	0	0	0
T110	2920	0	0	0
T111	2874	0	0	0
T112	4680	0	0	0
T177	0	2	0	0
T178	0	15	0	0
T179	0	5	0	0
T180	0	11	0	0
T181	0	1	0	0
T182	0	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106926561	413	0	0
T5	1184	1	0	0
T6	1616	0	0	0
T22	0	9	0	0
T30	1412	0	0	0
T31	1492	0	0	0
T32	1523	0	0	0
T33	2162	0	0	0
T34	959	0	0	0
T35	952	0	0	0
T36	1413	0	0	0
T46	0	11	0	0
T54	1692	0	0	0
T67	0	14	0	0
T70	3406	0	0	0
T71	3030	0	0	0
T88	0	6	0	0
T98	16536	0	0	0
T100	2526	13	0	0
T105	2228	0	0	0
T106	2694	0	0	0
T109	3724	0	0	0
T110	2920	0	0	0
T111	2874	0	0	0
T112	4680	0	0	0
T177	0	2	0	0
T178	0	15	0	0
T179	0	5	0	0
T180	0	11	0	0
T181	0	1	0	0
T182	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35642187	140	0	0
StatusRise_A	35642187	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	140	0	0
T5	1184	1	0	0
T6	1616	0	0	0
T22	0	3	0	0
T30	1412	0	0	0
T31	1492	0	0	0
T32	1523	0	0	0
T33	2162	0	0	0
T34	959	0	0	0
T35	952	0	0	0
T36	1413	0	0	0
T46	0	4	0	0
T54	1692	0	0	0
T67	0	5	0	0
T88	0	2	0	0
T100	0	6	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	140	0	0
T5	1184	1	0	0
T6	1616	0	0	0
T22	0	3	0	0
T30	1412	0	0	0
T31	1492	0	0	0
T32	1523	0	0	0
T33	2162	0	0	0
T34	959	0	0	0
T35	952	0	0	0
T36	1413	0	0	0
T46	0	4	0	0
T54	1692	0	0	0
T67	0	5	0	0
T88	0	2	0	0
T100	0	6	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35642187	131	0	0
StatusRise_A	35642187	131	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	131	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	1703	0	0	0
T71	1515	0	0	0
T88	0	2	0	0
T98	8268	0	0	0
T100	1263	3	0	0
T105	1114	0	0	0
T106	1347	0	0	0
T109	1862	0	0	0
T110	1460	0	0	0
T111	1437	0	0	0
T112	2340	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	131	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	1703	0	0	0
T71	1515	0	0	0
T88	0	2	0	0
T98	8268	0	0	0
T100	1263	3	0	0
T105	1114	0	0	0
T106	1347	0	0	0
T109	1862	0	0	0
T110	1460	0	0	0
T111	1437	0	0	0
T112	2340	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35642187	142	0	0
StatusRise_A	35642187	142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	142	0	0
T22	0	3	0	0
T46	0	3	0	0
T67	0	5	0	0
T70	1703	0	0	0
T71	1515	0	0	0
T88	0	2	0	0
T98	8268	0	0	0
T100	1263	4	0	0
T105	1114	0	0	0
T106	1347	0	0	0
T109	1862	0	0	0
T110	1460	0	0	0
T111	1437	0	0	0
T112	2340	0	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	1	0	0
T180	0	3	0	0
T182	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35642187	142	0	0
T22	0	3	0	0
T46	0	3	0	0
T67	0	5	0	0
T70	1703	0	0	0
T71	1515	0	0	0
T88	0	2	0	0
T98	8268	0	0	0
T100	1263	4	0	0
T105	1114	0	0	0
T106	1347	0	0	0
T109	1862	0	0	0
T110	1460	0	0	0
T111	1437	0	0	0
T112	2340	0	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	1	0	0
T180	0	3	0	0
T182	0	2	0	0