Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T100,T98
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	928889698	32985	0	0
CgEnOn_A	928889698	23860	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	928889698	32985	0	0
T4	4396	3	0	0
T5	3085	4	0	0
T6	4338	39	0	0
T22	0	15	0	0
T30	15077	7	0	0
T31	7963	5	0	0
T32	4142	3	0	0
T33	5957	5	0	0
T34	8934	3	0	0
T35	5154	21	0	0
T36	15713	3	0	0
T46	0	20	0	0
T54	1781	1	0	0
T67	0	20	0	0
T70	57041	0	0	0
T71	29182	0	0	0
T88	0	10	0	0
T98	65915	0	0	0
T100	5114	21	0	0
T105	4876	0	0	0
T106	6187	0	0	0
T109	36467	0	0	0
T110	6175	0	0	0
T111	3064	0	0	0
T112	5189	0	0	0
T178	0	25	0	0
T179	0	10	0	0
T180	0	20	0	0
T181	0	5	0	0
T182	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	928889698	23860	0	0
T5	1175	1	0	0
T6	4338	36	0	0
T22	0	18	0	0
T30	15077	4	0	0
T31	7963	2	0	0
T32	4142	0	0	0
T33	5957	2	0	0
T34	8934	0	0	0
T35	5154	18	0	0
T36	15713	0	0	0
T44	0	41	0	0
T46	0	32	0	0
T50	0	3	0	0
T54	4735	4	0	0
T67	0	20	0	0
T69	12372	0	0	0
T70	57041	0	0	0
T71	29182	0	0	0
T88	0	10	0	0
T98	65915	0	0	0
T100	5114	30	0	0
T105	4876	0	0	0
T106	6187	0	0	0
T109	36467	0	0	0
T110	6175	0	0	0
T111	3064	0	0	0
T112	5189	0	0	0
T136	0	3	0	0
T162	0	31	0	0
T178	0	25	0	0
T179	0	10	0	0
T180	0	20	0	0
T181	0	5	0	0
T182	0	25	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T98,T99
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	38935348	150	0	0
CgEnOn_A	38935348	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38935348	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	13475	0	0	0
T71	6826	0	0	0
T88	0	2	0	0
T98	13657	0	0	0
T100	1128	3	0	0
T105	1059	0	0	0
T106	1398	0	0	0
T109	8086	0	0	0
T110	1349	0	0	0
T111	674	0	0	0
T112	1179	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38935348	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	13475	0	0	0
T71	6826	0	0	0
T88	0	2	0	0
T98	13657	0	0	0
T100	1128	3	0	0
T105	1059	0	0	0
T106	1398	0	0	0
T109	8086	0	0	0
T110	1349	0	0	0
T111	674	0	0	0
T112	1179	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T98,T99
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19467275	150	0	0
CgEnOn_A	19467275	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	6735	0	0	0
T71	3413	0	0	0
T88	0	2	0	0
T98	6835	0	0	0
T100	564	3	0	0
T105	530	0	0	0
T106	699	0	0	0
T109	4043	0	0	0
T110	674	0	0	0
T111	337	0	0	0
T112	588	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	6735	0	0	0
T71	3413	0	0	0
T88	0	2	0	0
T98	6835	0	0	0
T100	564	3	0	0
T105	530	0	0	0
T106	699	0	0	0
T109	4043	0	0	0
T110	674	0	0	0
T111	337	0	0	0
T112	588	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T98,T99
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19467275	150	0	0
CgEnOn_A	19467275	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	6735	0	0	0
T71	3413	0	0	0
T88	0	2	0	0
T98	6835	0	0	0
T100	564	3	0	0
T105	530	0	0	0
T106	699	0	0	0
T109	4043	0	0	0
T110	674	0	0	0
T111	337	0	0	0
T112	588	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	6735	0	0	0
T71	3413	0	0	0
T88	0	2	0	0
T98	6835	0	0	0
T100	564	3	0	0
T105	530	0	0	0
T106	699	0	0	0
T109	4043	0	0	0
T110	674	0	0	0
T111	337	0	0	0
T112	588	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T98,T99
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19467275	150	0	0
CgEnOn_A	19467275	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	6735	0	0	0
T71	3413	0	0	0
T88	0	2	0	0
T98	6835	0	0	0
T100	564	3	0	0
T105	530	0	0	0
T106	699	0	0	0
T109	4043	0	0	0
T110	674	0	0	0
T111	337	0	0	0
T112	588	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	6735	0	0	0
T71	3413	0	0	0
T88	0	2	0	0
T98	6835	0	0	0
T100	564	3	0	0
T105	530	0	0	0
T106	699	0	0	0
T109	4043	0	0	0
T110	674	0	0	0
T111	337	0	0	0
T112	588	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T98,T99
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	79636599	150	0	0
CgEnOn_A	79636599	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79636599	150	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	23361	0	0	0
T71	12117	0	0	0
T88	0	2	0	0
T98	31753	0	0	0
T100	2294	3	0	0
T105	2227	0	0	0
T106	2692	0	0	0
T109	16252	0	0	0
T110	2804	0	0	0
T111	1379	0	0	0
T112	2246	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79636599	135	0	0
T22	0	3	0	0
T46	0	4	0	0
T67	0	4	0	0
T70	23361	0	0	0
T71	12117	0	0	0
T88	0	2	0	0
T98	31753	0	0	0
T100	2294	3	0	0
T105	2227	0	0	0
T106	2692	0	0	0
T109	16252	0	0	0
T110	2804	0	0	0
T111	1379	0	0	0
T112	2246	0	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0
T181	0	1	0	0
T182	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T100,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88248330	142	0	0
CgEnOn_A	88248330	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	142	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T22	0	3	0	0
T30	5652	0	0	0
T31	2986	0	0	0
T32	1553	0	0	0
T33	2253	0	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T46	0	4	0	0
T54	1781	0	0	0
T67	0	5	0	0
T88	0	2	0	0
T100	0	6	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	140	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T22	0	3	0	0
T30	5652	0	0	0
T31	2986	0	0	0
T32	1553	0	0	0
T33	2253	0	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T46	0	4	0	0
T54	1781	0	0	0
T67	0	5	0	0
T88	0	2	0	0
T100	0	6	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T100,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88248330	142	0	0
CgEnOn_A	88248330	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	142	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T22	0	3	0	0
T30	5652	0	0	0
T31	2986	0	0	0
T32	1553	0	0	0
T33	2253	0	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T46	0	4	0	0
T54	1781	0	0	0
T67	0	5	0	0
T88	0	2	0	0
T100	0	6	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	140	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T22	0	3	0	0
T30	5652	0	0	0
T31	2986	0	0	0
T32	1553	0	0	0
T33	2253	0	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T46	0	4	0	0
T54	1781	0	0	0
T67	0	5	0	0
T88	0	2	0	0
T100	0	6	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T98,T99
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	42193362	148	0	0
CgEnOn_A	42193362	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42193362	148	0	0
T22	0	3	0	0
T46	0	3	0	0
T67	0	5	0	0
T70	11681	0	0	0
T71	6058	0	0	0
T88	0	2	0	0
T98	15877	0	0	0
T100	1105	4	0	0
T105	1114	0	0	0
T106	1347	0	0	0
T109	8126	0	0	0
T110	1402	0	0	0
T111	689	0	0	0
T112	1123	0	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	1	0	0
T180	0	3	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42193362	143	0	0
T22	0	3	0	0
T46	0	3	0	0
T67	0	5	0	0
T70	11681	0	0	0
T71	6058	0	0	0
T88	0	2	0	0
T98	15877	0	0	0
T100	1105	4	0	0
T105	1114	0	0	0
T106	1347	0	0	0
T109	8126	0	0	0
T110	1402	0	0	0
T111	689	0	0	0
T112	1123	0	0	0
T177	0	1	0	0
T178	0	5	0	0
T179	0	1	0	0
T180	0	3	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T46,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19467275	5451	0	0
CgEnOn_A	19467275	3186	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	5451	0	0
T4	663	1	0	0
T5	258	1	0	0
T6	369	13	0	0
T30	1333	2	0	0
T31	704	1	0	0
T32	366	1	0	0
T33	514	1	0	0
T34	815	1	0	0
T35	450	7	0	0
T36	1388	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19467275	3186	0	0
T6	369	12	0	0
T22	0	3	0	0
T30	1333	1	0	0
T31	704	0	0	0
T32	366	0	0	0
T33	514	0	0	0
T34	815	0	0	0
T35	450	6	0	0
T36	1388	0	0	0
T44	0	16	0	0
T46	0	4	0	0
T54	415	1	0	0
T69	1904	0	0	0
T100	0	3	0	0
T136	0	1	0	0
T162	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T46,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	38935348	5453	0	0
CgEnOn_A	38935348	3188	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38935348	5453	0	0
T4	1326	1	0	0
T5	515	1	0	0
T6	738	13	0	0
T30	2666	2	0	0
T31	1407	1	0	0
T32	732	1	0	0
T33	1028	1	0	0
T34	1630	1	0	0
T35	899	7	0	0
T36	2775	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38935348	3188	0	0
T6	738	12	0	0
T30	2666	1	0	0
T31	1407	0	0	0
T32	732	0	0	0
T33	1028	0	0	0
T34	1630	0	0	0
T35	899	6	0	0
T36	2775	0	0	0
T44	0	12	0	0
T46	0	4	0	0
T50	0	1	0	0
T54	829	1	0	0
T69	3812	0	0	0
T100	0	3	0	0
T136	0	1	0	0
T162	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T46,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	79636599	5478	0	0
CgEnOn_A	79636599	3198	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79636599	5478	0	0
T4	2407	1	0	0
T5	1137	1	0	0
T6	1583	13	0	0
T30	5426	2	0	0
T31	2866	1	0	0
T32	1491	1	0	0
T33	2162	1	0	0
T34	3178	1	0	0
T35	1864	7	0	0
T36	5657	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79636599	3198	0	0
T6	1583	12	0	0
T30	5426	1	0	0
T31	2866	0	0	0
T32	1491	0	0	0
T33	2162	0	0	0
T34	3178	0	0	0
T35	1864	6	0	0
T36	5657	0	0	0
T44	0	13	0	0
T46	0	4	0	0
T50	0	1	0	0
T54	1710	1	0	0
T69	6656	0	0	0
T100	0	3	0	0
T136	0	1	0	0
T162	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T100,T46,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	42193362	5459	0	0
CgEnOn_A	42193362	3176	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42193362	5459	0	0
T4	1203	1	0	0
T5	568	1	0	0
T6	791	14	0	0
T30	2713	2	0	0
T31	1433	1	0	0
T32	745	1	0	0
T33	1081	1	0	0
T34	1589	1	0	0
T35	932	6	0	0
T36	2828	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42193362	3176	0	0
T6	791	13	0	0
T30	2713	1	0	0
T31	1433	0	0	0
T32	745	0	0	0
T33	1081	0	0	0
T34	1589	0	0	0
T35	932	5	0	0
T36	2828	0	0	0
T44	0	12	0	0
T46	0	3	0	0
T50	0	1	0	0
T54	855	1	0	0
T69	3327	0	0	0
T100	0	4	0	0
T136	0	1	0	0
T162	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T100,T98
1	0	Covered	T30,T31,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88248330	2483	0	0
CgEnOn_A	88248330	2481	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2483	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	2	0	0
T32	1553	0	0	0
T33	2253	2	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T45	0	2	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	7	0	0
T110	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2481	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	2	0	0
T32	1553	0	0	0
T33	2253	2	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T45	0	2	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	7	0	0
T110	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T100,T98
1	0	Covered	T30,T31,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88248330	2532	0	0
CgEnOn_A	88248330	2530	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2532	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	3	0	0
T32	1553	0	0	0
T33	2253	4	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	7	0	0
T110	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2530	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	3	0	0
T32	1553	0	0	0
T33	2253	4	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	7	0	0
T110	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T100,T98
1	0	Covered	T30,T31,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88248330	2506	0	0
CgEnOn_A	88248330	2504	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2506	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	2	0	0
T32	1553	0	0	0
T33	2253	6	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T46	0	4	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	6	0	0
T110	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2504	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	2	0	0
T32	1553	0	0	0
T33	2253	6	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T46	0	4	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	6	0	0
T110	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T100,T98
1	0	Covered	T30,T31,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88248330	2441	0	0
CgEnOn_A	88248330	2439	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2441	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	3	0	0
T32	1553	0	0	0
T33	2253	4	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T45	0	4	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	6	0	0
T110	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88248330	2439	0	0
T5	1175	1	0	0
T6	1648	0	0	0
T30	5652	1	0	0
T31	2986	3	0	0
T32	1553	0	0	0
T33	2253	4	0	0
T34	3311	0	0	0
T35	1941	0	0	0
T36	5893	0	0	0
T45	0	4	0	0
T50	0	1	0	0
T54	1781	1	0	0
T100	0	6	0	0
T109	0	6	0	0
T110	0	3	0	0