Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	205092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

471179

1

T5

9

T6

30

T24

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	199221	1			T6	42		T24	9		T25	16
values[0x0]	226831	1			T5	19		T6	21		T24	10
values[0x1]	250219	1			T5	22		T6	18		T24	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142630	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

533641

1

T5

15

T6

35

T24

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2265	1			T17	2		T213	1		T23	2
valid_sources[0x01]	2255	1			T1	1		T17	2		T23	4
valid_sources[0x02]	2967	1			T98	2		T17	1		T19	1
valid_sources[0x03]	2327	1			T24	1		T28	1		T29	1
valid_sources[0x04]	2162	1			T6	3		T77	2		T133	2
valid_sources[0x05]	2596	1			T17	1		T22	1		T23	5
valid_sources[0x06]	2866	1			T6	4		T24	1		T16	1
valid_sources[0x07]	2975	1			T25	5		T98	1		T17	4
valid_sources[0x08]	2221	1			T54	1		T98	5		T17	3
valid_sources[0x09]	3477	1			T17	1		T49	3		T23	3
valid_sources[0x0a]	3215	1			T27	1		T78	1		T135	1
valid_sources[0x0b]	1947	1			T6	3		T27	1		T74	6
valid_sources[0x0c]	2200	1			T1	2		T23	3		T137	1
valid_sources[0x0d]	3204	1			T22	3		T49	2		T23	4
valid_sources[0x0e]	2158	1			T24	2		T134	1		T16	1
valid_sources[0x0f]	2702	1			T98	3		T1	1		T21	1
valid_sources[0x10]	2023	1			T27	3		T135	1		T1	1
valid_sources[0x11]	2319	1			T6	1		T19	2		T23	2
valid_sources[0x12]	2627	1			T1	2		T137	1		T212	1
valid_sources[0x13]	3150	1			T3	11		T17	1		T19	6
valid_sources[0x14]	2443	1			T1	1		T17	1		T21	4
valid_sources[0x15]	2562	1			T29	1		T135	4		T17	2
valid_sources[0x16]	2224	1			T28	1		T29	1		T74	15
valid_sources[0x17]	2399	1			T134	5		T49	1		T23	3
valid_sources[0x18]	3425	1			T27	1		T17	1		T22	1
valid_sources[0x19]	2604	1			T5	1		T78	1		T135	1
valid_sources[0x1a]	1969	1			T5	1		T24	1		T79	5
valid_sources[0x1b]	2833	1			T135	3		T17	2		T49	1
valid_sources[0x1c]	2306	1			T5	2		T27	1		T77	1
valid_sources[0x1d]	2501	1			T24	3		T27	1		T28	1
valid_sources[0x1e]	2887	1			T6	1		T29	1		T77	1
valid_sources[0x1f]	2796	1			T5	1		T6	3		T78	1
valid_sources[0x20]	2481	1			T28	1		T78	1		T1	2
valid_sources[0x21]	2743	1			T23	2		T212	1		T44	1
valid_sources[0x22]	2525	1			T6	4		T27	1		T17	2
valid_sources[0x23]	2575	1			T135	1		T133	2		T17	1
valid_sources[0x24]	2118	1			T133	2		T17	1		T19	1
valid_sources[0x25]	2467	1			T6	3		T27	1		T19	1
valid_sources[0x26]	3165	1			T1	1		T17	1		T21	1
valid_sources[0x27]	3259	1			T27	1		T1	1		T16	2
valid_sources[0x28]	2060	1			T23	1		T80	5		T214	1
valid_sources[0x29]	2369	1			T54	1		T134	1		T98	2
valid_sources[0x2a]	2920	1			T6	6		T1	1		T17	1
valid_sources[0x2b]	2658	1			T77	1		T1	1		T17	1
valid_sources[0x2c]	2370	1			T25	4		T17	1		T19	1
valid_sources[0x2d]	2243	1			T135	1		T1	2		T17	1
valid_sources[0x2e]	1791	1			T27	1		T135	2		T23	2
valid_sources[0x2f]	2221	1			T17	2		T50	1		T23	6
valid_sources[0x30]	3241	1			T1	1		T23	2		T215	1
valid_sources[0x31]	2281	1			T98	10		T23	12		T212	1
valid_sources[0x32]	2362	1			T135	1		T98	3		T16	1
valid_sources[0x33]	3354	1			T21	1		T49	2		T23	4
valid_sources[0x34]	2754	1			T29	1		T77	3		T17	1
valid_sources[0x35]	2461	1			T27	1		T29	1		T17	1
valid_sources[0x36]	2095	1			T5	1		T27	1		T134	2
valid_sources[0x37]	4756	1			T27	2		T134	1		T17	2
valid_sources[0x38]	2220	1			T28	1		T79	3		T17	3
valid_sources[0x39]	2369	1			T27	1		T133	1		T17	3
valid_sources[0x3a]	2767	1			T6	3		T28	1		T1	2
valid_sources[0x3b]	2167	1			T98	1		T1	1		T19	1
valid_sources[0x3c]	3074	1			T135	3		T1	2		T19	1
valid_sources[0x3d]	2658	1			T29	1		T134	1		T17	1
valid_sources[0x3e]	2266	1			T27	3		T75	4		T100	3
valid_sources[0x3f]	2363	1			T27	8		T17	1		T49	3
valid_sources[0x40]	3308	1			T6	2		T28	1		T72	7
valid_sources[0x41]	2535	1			T27	1		T134	2		T22	1
valid_sources[0x42]	2886	1			T25	17		T27	1		T134	1
valid_sources[0x43]	2830	1			T5	2		T22	2		T49	3
valid_sources[0x44]	4380	1			T24	1		T27	1		T22	1
valid_sources[0x45]	2722	1			T77	1		T22	1		T23	2
valid_sources[0x46]	2438	1			T29	1		T17	1		T23	5
valid_sources[0x47]	2638	1			T5	1		T16	1		T19	3
valid_sources[0x48]	2836	1			T27	4		T54	1		T17	1
valid_sources[0x49]	2237	1			T73	24		T49	1		T23	2
valid_sources[0x4a]	2266	1			T27	2		T17	2		T23	1
valid_sources[0x4b]	2192	1			T5	1		T29	1		T1	1
valid_sources[0x4c]	2602	1			T27	1		T29	1		T17	1
valid_sources[0x4d]	6280	1			T27	1		T77	1		T134	3
valid_sources[0x4e]	2871	1			T5	2		T77	6		T133	6
valid_sources[0x4f]	2080	1			T25	4		T27	2		T98	1
valid_sources[0x50]	2095	1			T54	1		T1	1		T16	2
valid_sources[0x51]	2194	1			T17	1		T23	5		T137	1
valid_sources[0x52]	2184	1			T17	1		T21	1		T23	4
valid_sources[0x53]	2481	1			T6	3		T77	1		T17	1
valid_sources[0x54]	2973	1			T27	1		T23	6		T137	2
valid_sources[0x55]	2967	1			T28	1		T17	1		T49	1
valid_sources[0x56]	2457	1			T28	1		T135	1		T16	1
valid_sources[0x57]	2287	1			T17	1		T22	1		T23	2
valid_sources[0x58]	2918	1			T78	1		T17	1		T19	1
valid_sources[0x59]	2631	1			T29	1		T22	1		T23	2
valid_sources[0x5a]	2723	1			T27	1		T17	2		T23	2
valid_sources[0x5b]	2009	1			T24	1		T29	2		T16	1
valid_sources[0x5c]	2543	1			T77	3		T134	1		T17	1
valid_sources[0x5d]	2659	1			T5	2		T25	2		T27	3
valid_sources[0x5e]	2226	1			T28	1		T17	1		T23	6
valid_sources[0x5f]	2609	1			T6	1		T27	1		T77	6
valid_sources[0x60]	2435	1			T6	2		T17	1		T49	1
valid_sources[0x61]	2613	1			T5	1		T24	1		T77	7
valid_sources[0x62]	2290	1			T16	1		T23	1		T212	1
valid_sources[0x63]	2789	1			T1	2		T19	2		T23	4
valid_sources[0x64]	2488	1			T27	1		T17	1		T49	1
valid_sources[0x65]	2534	1			T28	1		T98	1		T1	1
valid_sources[0x66]	2888	1			T134	1		T16	1		T17	1
valid_sources[0x67]	2309	1			T5	1		T1	1		T19	1
valid_sources[0x68]	2564	1			T28	1		T30	1		T19	1
valid_sources[0x69]	2383	1			T6	3		T28	1		T17	1
valid_sources[0x6a]	2407	1			T6	2		T132	1		T23	2
valid_sources[0x6b]	2510	1			T100	1		T17	1		T22	1
valid_sources[0x6c]	2370	1			T24	2		T29	1		T135	1
valid_sources[0x6d]	2426	1			T77	1		T17	3		T23	3
valid_sources[0x6e]	3297	1			T17	2		T49	2		T23	3
valid_sources[0x6f]	2395	1			T6	7		T17	3		T23	2
valid_sources[0x70]	2755	1			T27	1		T16	1		T17	1
valid_sources[0x71]	3152	1			T133	1		T134	2		T16	1
valid_sources[0x72]	2822	1			T6	3		T98	1		T17	1
valid_sources[0x73]	2581	1			T24	2		T28	1		T17	1
valid_sources[0x74]	2211	1			T1	1		T19	2		T22	2
valid_sources[0x75]	2755	1			T6	1		T28	1		T29	2
valid_sources[0x76]	2521	1			T17	1		T19	1		T22	1
valid_sources[0x77]	2964	1			T5	1		T77	1		T135	2
valid_sources[0x78]	2939	1			T16	1		T91	15		T23	4
valid_sources[0x79]	2315	1			T28	1		T77	2		T132	3
valid_sources[0x7a]	2416	1			T29	1		T17	1		T21	1
valid_sources[0x7b]	2365	1			T1	1		T17	1		T22	1
valid_sources[0x7c]	3056	1			T77	3		T78	1		T17	1
valid_sources[0x7d]	2078	1			T27	2		T79	2		T17	1
valid_sources[0x7e]	3181	1			T28	1		T135	6		T133	4
valid_sources[0x7f]	3317	1			T28	1		T19	1		T21	1
valid_sources[0x80]	2705	1			T27	1		T16	1		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

132791

1

T6

15

T24

8

T25

7

values[0x0]

all_enables

biggest_size

181921

1

T5

8

T6

10

T24

6

values[0x1]

all_enables

biggest_size

156467

1

T5

1

T6

5

T24

2