Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T74,T18
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T72
1	0	Covered	T4,T76,T20
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	166545930	8381	0	0
GateOpen_A	166545930	14802	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166545930	8381	0	0
T4	2827	7	0	0
T5	3681	46	0	0
T6	14550	4	0	0
T18	0	14	0	0
T19	0	4	0	0
T20	0	17	0	0
T24	3885	0	0	0
T25	4597	0	0	0
T26	16934	0	0	0
T27	9568	0	0	0
T28	13074	0	0	0
T29	5395	0	0	0
T30	6483	0	0	0
T72	0	4	0	0
T74	0	16	0	0
T76	0	12	0	0
T77	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166545930	14802	0	0
T4	2827	11	0	0
T5	3681	46	0	0
T6	14550	8	0	0
T24	3885	4	0	0
T25	4597	4	0	0
T26	16934	4	0	0
T27	9568	4	0	0
T28	13074	4	0	0
T29	5395	4	0	0
T30	6483	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T74,T18
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T72
1	0	Covered	T4,T76,T20
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	17969412	2001	0	0
GateOpen_A	17969412	3602	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969412	2001	0	0
T4	310	2	0	0
T5	389	11	0	0
T6	1613	1	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	0	5	0	0
T24	585	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1057	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	783	0	0	0
T72	0	1	0	0
T74	0	4	0	0
T76	0	3	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969412	3602	0	0
T4	310	3	0	0
T5	389	11	0	0
T6	1613	2	0	0
T24	585	1	0	0
T25	519	1	0	0
T26	1929	1	0	0
T27	1057	1	0	0
T28	1444	1	0	0
T29	635	1	0	0
T30	783	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T74,T18
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T72
1	0	Covered	T4,T76,T20
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	35939355	2147	0	0
GateOpen_A	35939355	3747	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35939355	2147	0	0
T4	620	2	0	0
T5	778	12	0	0
T6	3225	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	5	0	0
T24	1169	0	0	0
T25	1039	0	0	0
T26	3860	0	0	0
T27	2113	0	0	0
T28	2888	0	0	0
T29	1270	0	0	0
T30	1569	0	0	0
T72	0	1	0	0
T74	0	4	0	0
T76	0	3	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35939355	3747	0	0
T4	620	3	0	0
T5	778	12	0	0
T6	3225	2	0	0
T24	1169	1	0	0
T25	1039	1	0	0
T26	3860	1	0	0
T27	2113	1	0	0
T28	2888	1	0	0
T29	1270	1	0	0
T30	1569	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T74,T18
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T72
1	0	Covered	T4,T76,T20
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	73575584	2133	0	0
GateOpen_A	73575584	3742	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73575584	2133	0	0
T4	1292	2	0	0
T5	1676	12	0	0
T6	6474	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	5	0	0
T24	1421	0	0	0
T25	2026	0	0	0
T26	7430	0	0	0
T27	4265	0	0	0
T28	5828	0	0	0
T29	2327	0	0	0
T30	2754	0	0	0
T72	0	1	0	0
T74	0	4	0	0
T76	0	3	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73575584	3742	0	0
T4	1292	3	0	0
T5	1676	12	0	0
T6	6474	2	0	0
T24	1421	1	0	0
T25	2026	1	0	0
T26	7430	1	0	0
T27	4265	1	0	0
T28	5828	1	0	0
T29	2327	1	0	0
T30	2754	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T74,T18
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T72
1	0	Covered	T4,T76,T20
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	39061579	2100	0	0
GateOpen_A	39061579	3711	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39061579	2100	0	0
T4	605	1	0	0
T5	838	11	0	0
T6	3238	1	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	0	2	0	0
T24	710	0	0	0
T25	1013	0	0	0
T26	3715	0	0	0
T27	2133	0	0	0
T28	2914	0	0	0
T29	1163	0	0	0
T30	1377	0	0	0
T72	0	1	0	0
T74	0	4	0	0
T76	0	3	0	0
T77	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39061579	3711	0	0
T4	605	2	0	0
T5	838	11	0	0
T6	3238	2	0	0
T24	710	1	0	0
T25	1013	1	0	0
T26	3715	1	0	0
T27	2133	1	0	0
T28	2914	1	0	0
T29	1163	1	0	0
T30	1377	1	0	0