Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	195932535	35037	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195932535	35037	0	0
T1	124275	95	0	0
T2	132155	0	0	0
T3	77485	98	0	0
T8	0	79	0	0
T9	0	365	0	0
T10	0	192	0	0
T11	0	89	0	0
T12	0	368	0	0
T13	0	112	0	0
T14	0	40	0	0
T15	0	432	0	0
T16	69925	0	0	0
T17	128375	0	0	0
T18	5755	0	0	0
T19	8985	0	0	0
T20	5570	0	0	0
T21	14655	0	0	0
T22	13145	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39186507	5197	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	5197	0	0
T1	24855	12	0	0
T2	26431	0	0	0
T3	15497	17	0	0
T8	0	13	0	0
T9	0	47	0	0
T10	0	27	0	0
T11	0	14	0	0
T12	0	54	0	0
T13	0	14	0	0
T14	0	7	0	0
T15	0	65	0	0
T16	13985	0	0	0
T17	25675	0	0	0
T18	1151	0	0	0
T19	1797	0	0	0
T20	1114	0	0	0
T21	2931	0	0	0
T22	2629	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39186507	5072	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	5072	0	0
T1	24855	13	0	0
T2	26431	0	0	0
T3	15497	15	0	0
T8	0	13	0	0
T9	0	46	0	0
T10	0	27	0	0
T11	0	14	0	0
T12	0	51	0	0
T13	0	16	0	0
T14	0	7	0	0
T15	0	62	0	0
T16	13985	0	0	0
T17	25675	0	0	0
T18	1151	0	0	0
T19	1797	0	0	0
T20	1114	0	0	0
T21	2931	0	0	0
T22	2629	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39186507	7034	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	7034	0	0
T1	24855	19	0	0
T2	26431	0	0	0
T3	15497	20	0	0
T8	0	16	0	0
T9	0	72	0	0
T10	0	38	0	0
T11	0	18	0	0
T12	0	73	0	0
T13	0	23	0	0
T14	0	8	0	0
T15	0	87	0	0
T16	13985	0	0	0
T17	25675	0	0	0
T18	1151	0	0	0
T19	1797	0	0	0
T20	1114	0	0	0
T21	2931	0	0	0
T22	2629	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39186507	7056	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	7056	0	0
T1	24855	19	0	0
T2	26431	0	0	0
T3	15497	19	0	0
T8	0	16	0	0
T9	0	74	0	0
T10	0	38	0	0
T11	0	18	0	0
T12	0	74	0	0
T13	0	21	0	0
T14	0	8	0	0
T15	0	88	0	0
T16	13985	0	0	0
T17	25675	0	0	0
T18	1151	0	0	0
T19	1797	0	0	0
T20	1114	0	0	0
T21	2931	0	0	0
T22	2629	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39186507	10678	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	10678	0	0
T1	24855	32	0	0
T2	26431	0	0	0
T3	15497	27	0	0
T8	0	21	0	0
T9	0	126	0	0
T10	0	62	0	0
T11	0	25	0	0
T12	0	116	0	0
T13	0	38	0	0
T14	0	10	0	0
T15	0	130	0	0
T16	13985	0	0	0
T17	25675	0	0	0
T18	1151	0	0	0
T19	1797	0	0	0
T20	1114	0	0	0
T21	2931	0	0	0
T22	2629	0	0	0