Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T98,T16,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	39186507	36365345	0	0
AllClkBypReqTrue_A	39186507	96974	0	0
IoClkBypReqFalse_A	39186507	36309909	0	2412
IoClkBypReqTrue_A	39186507	147796	0	0
LcClkBypAckFalse_A	39186507	36375324	0	0
LcClkBypAckTrue_A	39186507	86995	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	36365345	0	0
T4	1328	1135	0	0
T5	1728	1574	0	0
T6	1685	1653	0	0
T24	1465	1323	0	0
T25	2025	1889	0	0
T26	1934	1671	0	0
T27	2220	2149	0	0
T28	1517	1481	0	0
T29	2326	1846	0	0
T30	2753	2279	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	96974	0	0
T21	0	366	0	0
T24	1465	45	0	0
T25	2025	0	0	0
T26	1934	206	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	262	0	0
T30	2753	325	0	0
T54	724	24	0	0
T72	1962	0	0	0
T73	1400	0	0	0
T79	0	63	0	0
T132	0	12	0	0
T133	0	251	0	0
T134	0	243	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	36309909	0	2412
T4	1328	1133	0	3
T5	1728	1572	0	3
T6	1685	1651	0	3
T24	1465	1335	0	3
T25	2025	1578	0	3
T26	1934	1610	0	3
T27	2220	2147	0	3
T28	1517	1479	0	3
T29	2326	1791	0	3
T30	2753	2132	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	147796	0	0
T24	1465	31	0	0
T25	2025	309	0	0
T26	1934	265	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	315	0	0
T30	2753	470	0	0
T54	724	24	0	0
T72	1962	0	0	0
T73	1400	0	0	0
T75	0	27	0	0
T79	0	50	0	0
T133	0	389	0	0
T134	0	304	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	36375324	0	0
T4	1328	1135	0	0
T5	1728	1574	0	0
T6	1685	1653	0	0
T24	1465	1342	0	0
T25	2025	1777	0	0
T26	1934	1796	0	0
T27	2220	2149	0	0
T28	1517	1481	0	0
T29	2326	1863	0	0
T30	2753	2307	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	86995	0	0
T21	0	242	0	0
T24	1465	26	0	0
T25	2025	112	0	0
T26	1934	81	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	245	0	0
T30	2753	297	0	0
T54	724	9	0	0
T72	1962	0	0	0
T73	1400	0	0	0
T79	0	29	0	0
T133	0	275	0	0
T134	0	172	0	0