Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	325696272	9284	0	0
TransStop_A	325696272	4706	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325696272	9284	0	0
T6	26980	4	0	0
T19	0	4	0	0
T22	0	27	0	0
T24	5920	0	0	0
T25	8440	0	0	0
T26	30956	0	0	0
T27	17772	29	0	0
T28	24284	14	0	0
T29	9696	0	0	0
T30	11476	0	0	0
T49	0	35	0	0
T54	15268	0	0	0
T72	13084	4	0	0
T77	0	4	0	0
T78	0	7	0	0
T135	0	18	0	0
T136	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	325696272	4706	0	0
T6	26980	4	0	0
T19	0	4	0	0
T22	0	8	0	0
T24	5920	0	0	0
T25	8440	0	0	0
T26	30956	0	0	0
T27	17772	9	0	0
T28	24284	9	0	0
T29	9696	0	0	0
T30	11476	0	0	0
T49	0	10	0	0
T54	15268	0	0	0
T72	13084	4	0	0
T77	0	4	0	0
T78	0	2	0	0
T135	0	13	0	0
T137	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81424068	2312	0	0
TransStop_A	81424068	1196	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	2312	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	8	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	8	0	0
T28	6071	4	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	10	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T135	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	1196	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	3	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	3	0	0
T28	6071	2	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	4	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T135	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81424068	2344	0	0
TransStop_A	81424068	1160	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	2344	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	6	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	7	0	0
T28	6071	3	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	11	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T135	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	1160	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	2	0	0
T28	6071	2	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	2	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T135	0	4	0	0
T137	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81424068	2348	0	0
TransStop_A	81424068	1200	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	2348	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	7	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	10	0	0
T28	6071	2	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	7	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T135	0	5	0	0
T136	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	1200	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	2	0	0
T28	6071	1	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	2	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T135	0	4	0	0
T137	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81424068	2280	0	0
TransStop_A	81424068	1150	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	2280	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	6	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	4	0	0
T28	6071	5	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	7	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T78	0	3	0	0
T135	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81424068	1150	0	0
T6	6745	1	0	0
T19	0	1	0	0
T22	0	1	0	0
T24	1480	0	0	0
T25	2110	0	0	0
T26	7739	0	0	0
T27	4443	2	0	0
T28	6071	4	0	0
T29	2424	0	0	0
T30	2869	0	0	0
T49	0	2	0	0
T54	3817	0	0	0
T72	3271	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T135	0	2	0	0