Line Coverage for Module :
prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T24 T25 T26
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T24 T25 T26
Line Coverage for Module :
prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
975128017 |
923939354 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
975128017 |
923939354 |
0 |
0 |
| T4 |
18282 |
15680 |
0 |
0 |
| T5 |
23790 |
21899 |
0 |
0 |
| T6 |
77839 |
76434 |
0 |
0 |
| T24 |
22211 |
21005 |
0 |
0 |
| T25 |
28955 |
27170 |
0 |
0 |
| T26 |
89956 |
87560 |
0 |
0 |
| T27 |
54560 |
52908 |
0 |
0 |
| T28 |
70003 |
68482 |
0 |
0 |
| T29 |
33580 |
30701 |
0 |
0 |
| T30 |
39989 |
38065 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T24 T25 T26
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T24 T25 T26
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
39186507 |
36464626 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
39186507 |
36464626 |
0 |
0 |
| T4 |
1328 |
1136 |
0 |
0 |
| T5 |
1728 |
1575 |
0 |
0 |
| T6 |
1685 |
1654 |
0 |
0 |
| T24 |
1465 |
1369 |
0 |
0 |
| T25 |
2025 |
1890 |
0 |
0 |
| T26 |
1934 |
1878 |
0 |
0 |
| T27 |
2220 |
2150 |
0 |
0 |
| T28 |
1517 |
1482 |
0 |
0 |
| T29 |
2326 |
2109 |
0 |
0 |
| T30 |
2753 |
2605 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T24 T25 T26
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T24 T25 T26
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
39186507 |
36464626 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
39186507 |
36464626 |
0 |
0 |
| T4 |
1328 |
1136 |
0 |
0 |
| T5 |
1728 |
1575 |
0 |
0 |
| T6 |
1685 |
1654 |
0 |
0 |
| T24 |
1465 |
1369 |
0 |
0 |
| T25 |
2025 |
1890 |
0 |
0 |
| T26 |
1934 |
1878 |
0 |
0 |
| T27 |
2220 |
2150 |
0 |
0 |
| T28 |
1517 |
1482 |
0 |
0 |
| T29 |
2326 |
2109 |
0 |
0 |
| T30 |
2753 |
2605 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T24 T25 T26
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
39186507 |
36464626 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
39186507 |
36464626 |
0 |
0 |
| T4 |
1328 |
1136 |
0 |
0 |
| T5 |
1728 |
1575 |
0 |
0 |
| T6 |
1685 |
1654 |
0 |
0 |
| T24 |
1465 |
1369 |
0 |
0 |
| T25 |
2025 |
1890 |
0 |
0 |
| T26 |
1934 |
1878 |
0 |
0 |
| T27 |
2220 |
2150 |
0 |
0 |
| T28 |
1517 |
1482 |
0 |
0 |
| T29 |
2326 |
2109 |
0 |
0 |
| T30 |
2753 |
2605 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
17969019 |
17458325 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
17969019 |
17458325 |
0 |
0 |
| T4 |
310 |
276 |
0 |
0 |
| T5 |
389 |
382 |
0 |
0 |
| T6 |
1612 |
1588 |
0 |
0 |
| T24 |
584 |
577 |
0 |
0 |
| T25 |
519 |
502 |
0 |
0 |
| T26 |
1929 |
1901 |
0 |
0 |
| T27 |
1056 |
1032 |
0 |
0 |
| T28 |
1444 |
1423 |
0 |
0 |
| T29 |
635 |
607 |
0 |
0 |
| T30 |
782 |
768 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
81423641 |
77009877 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
81423641 |
77009877 |
0 |
0 |
| T4 |
1338 |
1141 |
0 |
0 |
| T5 |
1745 |
1590 |
0 |
0 |
| T6 |
6744 |
6618 |
0 |
0 |
| T24 |
1480 |
1383 |
0 |
0 |
| T25 |
2109 |
1969 |
0 |
0 |
| T26 |
7739 |
7513 |
0 |
0 |
| T27 |
4443 |
4302 |
0 |
0 |
| T28 |
6070 |
5929 |
0 |
0 |
| T29 |
2424 |
2198 |
0 |
0 |
| T30 |
2868 |
2714 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
39061206 |
36956008 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
39061206 |
36956008 |
0 |
0 |
| T4 |
605 |
510 |
0 |
0 |
| T5 |
838 |
764 |
0 |
0 |
| T6 |
3237 |
3176 |
0 |
0 |
| T24 |
710 |
664 |
0 |
0 |
| T25 |
1012 |
945 |
0 |
0 |
| T26 |
3714 |
3606 |
0 |
0 |
| T27 |
2132 |
2064 |
0 |
0 |
| T28 |
2914 |
2847 |
0 |
0 |
| T29 |
1163 |
1055 |
0 |
0 |
| T30 |
1376 |
1302 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
73575126 |
69453000 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
73575126 |
69453000 |
0 |
0 |
| T4 |
1291 |
1101 |
0 |
0 |
| T5 |
1675 |
1526 |
0 |
0 |
| T6 |
6474 |
6353 |
0 |
0 |
| T24 |
1421 |
1327 |
0 |
0 |
| T25 |
2025 |
1890 |
0 |
0 |
| T26 |
7429 |
7212 |
0 |
0 |
| T27 |
4264 |
4130 |
0 |
0 |
| T28 |
5827 |
5692 |
0 |
0 |
| T29 |
2326 |
2109 |
0 |
0 |
| T30 |
2753 |
2605 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
35938955 |
34917449 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
35938955 |
34917449 |
0 |
0 |
| T4 |
619 |
550 |
0 |
0 |
| T5 |
777 |
763 |
0 |
0 |
| T6 |
3225 |
3177 |
0 |
0 |
| T24 |
1169 |
1155 |
0 |
0 |
| T25 |
1038 |
1004 |
0 |
0 |
| T26 |
3859 |
3804 |
0 |
0 |
| T27 |
2113 |
2065 |
0 |
0 |
| T28 |
2887 |
2846 |
0 |
0 |
| T29 |
1270 |
1215 |
0 |
0 |
| T30 |
1568 |
1540 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
17969019 |
17458325 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
17969019 |
17458325 |
0 |
0 |
| T4 |
310 |
276 |
0 |
0 |
| T5 |
389 |
382 |
0 |
0 |
| T6 |
1612 |
1588 |
0 |
0 |
| T24 |
584 |
577 |
0 |
0 |
| T25 |
519 |
502 |
0 |
0 |
| T26 |
1929 |
1901 |
0 |
0 |
| T27 |
1056 |
1032 |
0 |
0 |
| T28 |
1444 |
1423 |
0 |
0 |
| T29 |
635 |
607 |
0 |
0 |
| T30 |
782 |
768 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
81423641 |
77009877 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
81423641 |
77009877 |
0 |
0 |
| T4 |
1338 |
1141 |
0 |
0 |
| T5 |
1745 |
1590 |
0 |
0 |
| T6 |
6744 |
6618 |
0 |
0 |
| T24 |
1480 |
1383 |
0 |
0 |
| T25 |
2109 |
1969 |
0 |
0 |
| T26 |
7739 |
7513 |
0 |
0 |
| T27 |
4443 |
4302 |
0 |
0 |
| T28 |
6070 |
5929 |
0 |
0 |
| T29 |
2424 |
2198 |
0 |
0 |
| T30 |
2868 |
2714 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
17969019 |
17458325 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
17969019 |
17458325 |
0 |
0 |
| T4 |
310 |
276 |
0 |
0 |
| T5 |
389 |
382 |
0 |
0 |
| T6 |
1612 |
1588 |
0 |
0 |
| T24 |
584 |
577 |
0 |
0 |
| T25 |
519 |
502 |
0 |
0 |
| T26 |
1929 |
1901 |
0 |
0 |
| T27 |
1056 |
1032 |
0 |
0 |
| T28 |
1444 |
1423 |
0 |
0 |
| T29 |
635 |
607 |
0 |
0 |
| T30 |
782 |
768 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
17969019 |
17458325 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
17969019 |
17458325 |
0 |
0 |
| T4 |
310 |
276 |
0 |
0 |
| T5 |
389 |
382 |
0 |
0 |
| T6 |
1612 |
1588 |
0 |
0 |
| T24 |
584 |
577 |
0 |
0 |
| T25 |
519 |
502 |
0 |
0 |
| T26 |
1929 |
1901 |
0 |
0 |
| T27 |
1056 |
1032 |
0 |
0 |
| T28 |
1444 |
1423 |
0 |
0 |
| T29 |
635 |
607 |
0 |
0 |
| T30 |
782 |
768 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
35938955 |
34917449 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
35938955 |
34917449 |
0 |
0 |
| T4 |
619 |
550 |
0 |
0 |
| T5 |
777 |
763 |
0 |
0 |
| T6 |
3225 |
3177 |
0 |
0 |
| T24 |
1169 |
1155 |
0 |
0 |
| T25 |
1038 |
1004 |
0 |
0 |
| T26 |
3859 |
3804 |
0 |
0 |
| T27 |
2113 |
2065 |
0 |
0 |
| T28 |
2887 |
2846 |
0 |
0 |
| T29 |
1270 |
1215 |
0 |
0 |
| T30 |
1568 |
1540 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
73575126 |
69453000 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
73575126 |
69453000 |
0 |
0 |
| T4 |
1291 |
1101 |
0 |
0 |
| T5 |
1675 |
1526 |
0 |
0 |
| T6 |
6474 |
6353 |
0 |
0 |
| T24 |
1421 |
1327 |
0 |
0 |
| T25 |
2025 |
1890 |
0 |
0 |
| T26 |
7429 |
7212 |
0 |
0 |
| T27 |
4264 |
4130 |
0 |
0 |
| T28 |
5827 |
5692 |
0 |
0 |
| T29 |
2326 |
2109 |
0 |
0 |
| T30 |
2753 |
2605 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
39061206 |
36956008 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
39061206 |
36956008 |
0 |
0 |
| T4 |
605 |
510 |
0 |
0 |
| T5 |
838 |
764 |
0 |
0 |
| T6 |
3237 |
3176 |
0 |
0 |
| T24 |
710 |
664 |
0 |
0 |
| T25 |
1012 |
945 |
0 |
0 |
| T26 |
3714 |
3606 |
0 |
0 |
| T27 |
2132 |
2064 |
0 |
0 |
| T28 |
2914 |
2847 |
0 |
0 |
| T29 |
1163 |
1055 |
0 |
0 |
| T30 |
1376 |
1302 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
81423641 |
77009877 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
81423641 |
77009877 |
0 |
0 |
| T4 |
1338 |
1141 |
0 |
0 |
| T5 |
1745 |
1590 |
0 |
0 |
| T6 |
6744 |
6618 |
0 |
0 |
| T24 |
1480 |
1383 |
0 |
0 |
| T25 |
2109 |
1969 |
0 |
0 |
| T26 |
7739 |
7513 |
0 |
0 |
| T27 |
4443 |
4302 |
0 |
0 |
| T28 |
6070 |
5929 |
0 |
0 |
| T29 |
2424 |
2198 |
0 |
0 |
| T30 |
2868 |
2714 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
81423641 |
77009877 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
81423641 |
77009877 |
0 |
0 |
| T4 |
1338 |
1141 |
0 |
0 |
| T5 |
1745 |
1590 |
0 |
0 |
| T6 |
6744 |
6618 |
0 |
0 |
| T24 |
1480 |
1383 |
0 |
0 |
| T25 |
2109 |
1969 |
0 |
0 |
| T26 |
7739 |
7513 |
0 |
0 |
| T27 |
4443 |
4302 |
0 |
0 |
| T28 |
6070 |
5929 |
0 |
0 |
| T29 |
2424 |
2198 |
0 |
0 |
| T30 |
2868 |
2714 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
81423641 |
77009877 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
81423641 |
77009877 |
0 |
0 |
| T4 |
1338 |
1141 |
0 |
0 |
| T5 |
1745 |
1590 |
0 |
0 |
| T6 |
6744 |
6618 |
0 |
0 |
| T24 |
1480 |
1383 |
0 |
0 |
| T25 |
2109 |
1969 |
0 |
0 |
| T26 |
7739 |
7513 |
0 |
0 |
| T27 |
4443 |
4302 |
0 |
0 |
| T28 |
6070 |
5929 |
0 |
0 |
| T29 |
2424 |
2198 |
0 |
0 |
| T30 |
2868 |
2714 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
81423641 |
77009877 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
81423641 |
77009877 |
0 |
0 |
| T4 |
1338 |
1141 |
0 |
0 |
| T5 |
1745 |
1590 |
0 |
0 |
| T6 |
6744 |
6618 |
0 |
0 |
| T24 |
1480 |
1383 |
0 |
0 |
| T25 |
2109 |
1969 |
0 |
0 |
| T26 |
7739 |
7513 |
0 |
0 |
| T27 |
4443 |
4302 |
0 |
0 |
| T28 |
6070 |
5929 |
0 |
0 |
| T29 |
2424 |
2198 |
0 |
0 |
| T30 |
2868 |
2714 |
0 |
0 |