Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	40123261	498236	0	0
clk_enables_rd_A	40123261	7835	0	0
clk_hints_rd_A	40123261	7597	0	0
extclk_ctrl_rd_A	40123261	13782	0	0
extclk_ctrl_regwen_rd_A	40123261	6183	0	0
jitter_enable_rd_A	40123261	17472	0	0
jitter_regwen_rd_A	40123261	6343	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40123261	498236	0	0
T55	82175	3884	0	0
T56	215449	10895	0	0
T57	169835	6895	0	0
T58	0	5040	0	0
T59	0	6219	0	0
T60	0	8634	0	0
T61	0	2679	0	0
T62	0	10627	0	0
T63	0	5404	0	0
T64	0	832	0	0
T65	54950	0	0	0
T66	76077	0	0	0
T67	230490	0	0	0
T68	1983	0	0	0
T69	1455	0	0	0
T70	1969	0	0	0
T71	1227	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40123261	7835	0	0
T6	1685	2	0	0
T15	0	9	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T54	724	0	0	0
T72	1962	0	0	0
T77	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	9	0	0
T161	0	4	0	0
T162	0	3	0	0
T163	0	19	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40123261	7597	0	0
T6	1685	1	0	0
T15	0	2	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T54	724	0	0	0
T72	1962	0	0	0
T77	0	5	0	0
T157	0	3	0	0
T159	0	2	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	24	0	0
T164	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40123261	13782	0	0
T21	0	71	0	0
T30	2753	87	0	0
T50	0	13	0	0
T54	724	0	0	0
T72	1962	0	0	0
T73	1400	0	0	0
T74	1507	0	0	0
T75	1311	0	0	0
T76	974	0	0	0
T77	1806	0	0	0
T78	1309	0	0	0
T79	1309	0	0	0
T80	0	29	0	0
T165	0	48	0	0
T166	0	24	0	0
T167	0	19	0	0
T168	0	17	0	0
T169	0	50	0	0
T170	0	34	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40123261	6183	0	0
T31	41510	0	0	0
T35	49994	0	0	0
T51	86647	39	0	0
T52	10648	0	0	0
T53	17706	0	0	0
T60	0	278	0	0
T61	0	99	0	0
T65	0	29	0	0
T110	28501	0	0	0
T171	0	65	0	0
T172	0	21	0	0
T173	0	40	0	0
T174	0	48	0	0
T175	0	31	0	0
T176	0	54	0	0
T177	2007	0	0	0
T178	1381	0	0	0
T179	1333	0	0	0
T180	1655	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40123261	17472	0	0
T6	1685	114	0	0
T15	0	199	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T54	724	0	0	0
T72	1962	98	0	0
T77	0	102	0	0
T157	0	63	0	0
T158	0	88	0	0
T159	0	112	0	0
T160	0	128	0	0
T161	0	141	0	0
T164	0	119	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40123261	6343	0	0
T60	342108	351	0	0
T61	0	132	0	0
T181	0	194	0	0
T182	0	478	0	0
T183	0	520	0	0
T184	0	94	0	0
T185	0	68	0	0
T186	0	98	0	0
T187	0	847	0	0
T188	0	129	0	0
T189	1617	0	0	0
T190	985	0	0	0
T191	74071	0	0	0
T192	996	0	0	0
T193	1918	0	0	0
T194	1776	0	0	0
T195	2614	0	0	0
T196	1191	0	0	0
T197	2777	0	0	0