Unified Coverage Report :: Module :: prim_clock_meas

Module : prim_clock_meas

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_io_div2_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_io_div4_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_main_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67
tb.dut.u_usb_meas.u_meas	93.33	100.00	100.00		100.00	100.00	66.67

---

Module Instance : tb.dut.u_io_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_main_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_usb_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00	100.00		100.00	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	100.00	100.00		100.00	100.00	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	100.00	100.00				100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	87.50	100.00	100.00			100.00	50.00
u_ref_meas_en_sync	100.00	100.00				100.00
u_sync_ref	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_clock_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

87                        always_ff @(posedge clk_i or negedge rst_ni) begin
88         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
89         1/1                state_q <= StDisable;
           Tests:       T4 T5 T6 
90                          end else begin
91         1/1                state_q <= state_d;
           Tests:       T4 T5 T6 
92                          end
93                        end
94                      
95                        // The following fsm sequence ensures that even if the source
96                        // side changes the enable too quickly, the measurement controls
97                        // remain consistent.
98                        logic cnt_en;
99                        always_comb begin
100        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
101        1/1              cnt_en = '0;
           Tests:       T1 T2 T3 
102                     
103        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
104                     
105                           StDisable: begin
106        1/1                  if (en_i) begin
           Tests:       T1 T2 T3 
107        1/1                    state_d = StEnabling;
           Tests:       T1 T2 T3 
108                             end
                        MISSING_ELSE
109                           end
110                     
111                           StEnabling: begin
112        1/1                  if (en_ref_sync) begin
           Tests:       T1 T2 T3 
113        1/1                    state_d = StEnable;
           Tests:       T1 T3 T17 
114                             end
                        MISSING_ELSE
115                           end
116                     
117                           StEnable: begin
118        1/1                  cnt_en = 1'b1;
           Tests:       T1 T3 T17 
119        1/1                  if (!en_i) begin
           Tests:       T1 T3 T17 
120        1/1                    state_d = StDisabling;
           Tests:       T1 T3 T17 
121                             end
                        MISSING_ELSE
122                           end
123                     
124                           StDisabling: begin
125        1/1                  if (!en_ref_sync) begin
           Tests:       T1 T3 T17 
126        1/1                    state_d = StDisable;
           Tests:       T1 T3 T17 
127                             end
                        MISSING_ELSE
128                           end
129                     
130                           //VCS coverage off
131                           // pragma coverage off
132                           default:;
133                           //VCS coverage on
134                           // pragma coverage on
135                     
136                         endcase // unique case (state_q)
137                       end
138                     
139                       //////////////////////////
140                       // Input Clock Logic
141                       //////////////////////////
142                     
143                       logic valid_ref;
144                       logic valid;
145                       // The valid pulse causes the count to reset and start counting again
146                       // for each reference cycle.
147                       // The count obtained during the last reference cycle is used
148                       // to measure how fast/slow the input clock is.
149                       prim_pulse_sync u_sync_ref (
150                         .clk_src_i(clk_ref_i),
151                         .rst_src_ni(rst_ref_ni),
152                         .src_pulse_i(ref_en),
153                         .clk_dst_i(clk_i),
154                         .rst_dst_ni(rst_ni),
155                         .dst_pulse_o(valid_ref)
156                       );
157                     
158                     
159                       if (RefCnt == 1) begin : gen_degenerate_case
160                         // if reference count is one, cnt_ref is always 0.
161                         // So there is no need to maintain a counter, and
162                         // valid just becomes valid_ref
163        1/1              assign valid = valid_ref;
           Tests:       T1 T3 T17 
164                       end else begin : gen_normal_case
165                         logic [RefCntWidth-1:0] cnt_ref;
166                         assign valid = valid_ref & (int'(cnt_ref) == RefCnt - 1);
167                         always_ff @(posedge clk_i or negedge rst_ni) begin
168                           if (!rst_ni) begin
169                             cnt_ref <= '0;
170                           end else if (!cnt_en && |cnt_ref) begin
171                             cnt_ref <= '0;
172                           end else if (cnt_en && valid) begin
173                             cnt_ref <= '0;
174                           end else if (cnt_en && valid_ref) begin
175                             cnt_ref <= cnt_ref + 1'b1;
176                           end
177                         end
178                       end
179                     
180                       logic cnt_ovfl;
181                       logic [CntWidth-1:0] cnt;
182                       always_ff @(posedge clk_i or negedge rst_ni) begin
183        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
184        1/1                cnt <= '0;
           Tests:       T4 T5 T6 
185        1/1                cnt_ovfl <= '0;
           Tests:       T4 T5 T6 
186        1/1              end else if (!cnt_en && |cnt) begin
           Tests:       T4 T5 T6 
187        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
188        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
189        1/1              end else if (valid_o) begin
           Tests:       T4 T5 T6 
190        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
191        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
192        1/1              end else if (cnt_ovfl) begin
           Tests:       T4 T5 T6 
193        1/1                cnt <= '{default: '1};
           Tests:       T1 T3 T31 
194        1/1              end else if (cnt_en) begin
           Tests:       T4 T5 T6 
195        1/1                {cnt_ovfl, cnt} <= cnt + 1'b1;
           Tests:       T1 T3 T17 
196                         end
                        MISSING_ELSE
197                       end
198                     
199        1/1            assign valid_o = valid & |cnt;
           Tests:       T1 T3 T17 
200        1/1            assign fast_o = valid_o & ((cnt > max_cnt) | cnt_ovfl);
           Tests:       T1 T2 T3 
201        1/1            assign slow_o = valid_o & (cnt < min_cnt);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_clock_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T17

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T3,T17

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T31
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T3,T31

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T31
1	0	Covered	T1,T3,T31

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T17
1	1	Covered	T31,T9,T10

---

FSM Coverage for Module : prim_clock_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T4,T5,T6
StDisabling	120	Covered	T1,T3,T17
StEnable	113	Covered	T1,T3,T17
StEnabling	107	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T2,T3
StDisabling->StDisable	126	Covered	T1,T3,T17
StEnable->StDisabling	120	Covered	T1,T3,T17
StEnabling->StEnable	113	Covered	T1,T3,T17

---

Branch Coverage for Module : prim_clock_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

88             if (!rst_ni) begin
               -1-  
89               state_q <= StDisable;
                 ==>
90             end else begin
91               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

103            unique case (state_q)
                      -1-  
104        
105              StDisable: begin
106                if (en_i) begin
                   -2-  
107                  state_d = StEnabling;
                     ==>
108                end
                   MISSING_ELSE
                   ==>
109              end
110        
111              StEnabling: begin
112                if (en_ref_sync) begin
                   -3-  
113                  state_d = StEnable;
                     ==>
114                end
                   MISSING_ELSE
                   ==>
115              end
116        
117              StEnable: begin
118                cnt_en = 1'b1;
119                if (!en_i) begin
                   -4-  
120                  state_d = StDisabling;
                     ==>
121                end
                   MISSING_ELSE
                   ==>
122              end
123        
124              StDisabling: begin
125                if (!en_ref_sync) begin
                   -5-  
126                  state_d = StDisable;
                     ==>
127                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T2,T3
StDisable	0	-	-	-	Covered	T1,T2,T3
StEnabling	-	1	-	-	Covered	T1,T3,T17
StEnabling	-	0	-	-	Covered	T1,T2,T3
StEnable	-	-	1	-	Covered	T1,T3,T17
StEnable	-	-	0	-	Covered	T1,T3,T17
StDisabling	-	-	-	1	Covered	T1,T3,T17
StDisabling	-	-	-	0	Covered	T1,T3,T17

183            if (!rst_ni) begin
               -1-  
184              cnt <= '0;
                 ==>
185              cnt_ovfl <= '0;
186            end else if (!cnt_en && |cnt) begin
                        -2-  
187              cnt <= '0;
                 ==>
188              cnt_ovfl <= '0;
189            end else if (valid_o) begin
                        -3-  
190              cnt <= '0;
                 ==>
191              cnt_ovfl <= '0;
192            end else if (cnt_ovfl) begin
                        -4-  
193              cnt <= '{default: '1};
                 ==>
194            end else if (cnt_en) begin
                        -5-  
195              {cnt_ovfl, cnt} <= cnt + 1'b1;
                 ==>
196            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T6
0	1	-	-	-	Covered	T1,T3,T17
0	0	1	-	-	Covered	T1,T3,T17
0	0	0	1	-	Covered	T1,T3,T31
0	0	0	0	1	Covered	T1,T3,T17
0	0	0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_clock_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	247967947	0	0	0
RefCntVal_A	4020	4020	0	0
gen_timeout_assert.ClkRatios_A	4020	4020	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247967947	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4020	4020	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T24	5	5	0	0
T25	5	5	0	0
T26	5	5	0	0
T27	5	5	0	0
T28	5	5	0	0
T29	5	5	0	0
T30	5	5	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4020	4020	0	0
T4	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T24	5	5	0	0
T25	5	5	0	0
T26	5	5	0	0
T27	5	5	0	0
T28	5	5	0	0
T29	5	5	0	0
T30	5	5	0	0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

87                        always_ff @(posedge clk_i or negedge rst_ni) begin
88         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
89         1/1                state_q <= StDisable;
           Tests:       T4 T5 T6 
90                          end else begin
91         1/1                state_q <= state_d;
           Tests:       T4 T5 T6 
92                          end
93                        end
94                      
95                        // The following fsm sequence ensures that even if the source
96                        // side changes the enable too quickly, the measurement controls
97                        // remain consistent.
98                        logic cnt_en;
99                        always_comb begin
100        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
101        1/1              cnt_en = '0;
           Tests:       T1 T2 T3 
102                     
103        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
104                     
105                           StDisable: begin
106        1/1                  if (en_i) begin
           Tests:       T1 T2 T3 
107        1/1                    state_d = StEnabling;
           Tests:       T1 T2 T3 
108                             end
                        MISSING_ELSE
109                           end
110                     
111                           StEnabling: begin
112        1/1                  if (en_ref_sync) begin
           Tests:       T1 T2 T3 
113        1/1                    state_d = StEnable;
           Tests:       T1 T3 T17 
114                             end
                        MISSING_ELSE
115                           end
116                     
117                           StEnable: begin
118        1/1                  cnt_en = 1'b1;
           Tests:       T1 T3 T17 
119        1/1                  if (!en_i) begin
           Tests:       T1 T3 T17 
120        1/1                    state_d = StDisabling;
           Tests:       T1 T3 T17 
121                             end
                        MISSING_ELSE
122                           end
123                     
124                           StDisabling: begin
125        1/1                  if (!en_ref_sync) begin
           Tests:       T1 T3 T17 
126        1/1                    state_d = StDisable;
           Tests:       T1 T3 T17 
127                             end
                        MISSING_ELSE
128                           end
129                     
130                           //VCS coverage off
131                           // pragma coverage off
132                           default:;
133                           //VCS coverage on
134                           // pragma coverage on
135                     
136                         endcase // unique case (state_q)
137                       end
138                     
139                       //////////////////////////
140                       // Input Clock Logic
141                       //////////////////////////
142                     
143                       logic valid_ref;
144                       logic valid;
145                       // The valid pulse causes the count to reset and start counting again
146                       // for each reference cycle.
147                       // The count obtained during the last reference cycle is used
148                       // to measure how fast/slow the input clock is.
149                       prim_pulse_sync u_sync_ref (
150                         .clk_src_i(clk_ref_i),
151                         .rst_src_ni(rst_ref_ni),
152                         .src_pulse_i(ref_en),
153                         .clk_dst_i(clk_i),
154                         .rst_dst_ni(rst_ni),
155                         .dst_pulse_o(valid_ref)
156                       );
157                     
158                     
159                       if (RefCnt == 1) begin : gen_degenerate_case
160                         // if reference count is one, cnt_ref is always 0.
161                         // So there is no need to maintain a counter, and
162                         // valid just becomes valid_ref
163        1/1              assign valid = valid_ref;
           Tests:       T1 T3 T17 
164                       end else begin : gen_normal_case
165                         logic [RefCntWidth-1:0] cnt_ref;
166                         assign valid = valid_ref & (int'(cnt_ref) == RefCnt - 1);
167                         always_ff @(posedge clk_i or negedge rst_ni) begin
168                           if (!rst_ni) begin
169                             cnt_ref <= '0;
170                           end else if (!cnt_en && |cnt_ref) begin
171                             cnt_ref <= '0;
172                           end else if (cnt_en && valid) begin
173                             cnt_ref <= '0;
174                           end else if (cnt_en && valid_ref) begin
175                             cnt_ref <= cnt_ref + 1'b1;
176                           end
177                         end
178                       end
179                     
180                       logic cnt_ovfl;
181                       logic [CntWidth-1:0] cnt;
182                       always_ff @(posedge clk_i or negedge rst_ni) begin
183        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
184        1/1                cnt <= '0;
           Tests:       T4 T5 T6 
185        1/1                cnt_ovfl <= '0;
           Tests:       T4 T5 T6 
186        1/1              end else if (!cnt_en && |cnt) begin
           Tests:       T4 T5 T6 
187        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
188        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
189        1/1              end else if (valid_o) begin
           Tests:       T4 T5 T6 
190        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
191        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
192        1/1              end else if (cnt_ovfl) begin
           Tests:       T4 T5 T6 
193        1/1                cnt <= '{default: '1};
           Tests:       T3 T31 T9 
194        1/1              end else if (cnt_en) begin
           Tests:       T4 T5 T6 
195        1/1                {cnt_ovfl, cnt} <= cnt + 1'b1;
           Tests:       T1 T3 T17 
196                         end
                        MISSING_ELSE
197                       end
198                     
199        1/1            assign valid_o = valid & |cnt;
           Tests:       T1 T3 T17 
200        1/1            assign fast_o = valid_o & ((cnt > max_cnt) | cnt_ovfl);
           Tests:       T1 T2 T3 
201        1/1            assign slow_o = valid_o & (cnt < min_cnt);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T17

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T3,T17

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T9
1	0	Covered	T1,T3,T17
1	1	Covered	T3,T31,T9

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T31,T9
1	0	Covered	T3,T31,T9

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T17
1	1	Covered	T10,T11,T12

---

FSM Coverage for Instance : tb.dut.u_io_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T4,T5,T6
StDisabling	120	Covered	T1,T3,T17
StEnable	113	Covered	T1,T3,T17
StEnabling	107	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T2,T3
StDisabling->StDisable	126	Covered	T1,T3,T17
StEnable->StDisabling	120	Covered	T1,T3,T17
StEnabling->StEnable	113	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

88             if (!rst_ni) begin
               -1-  
89               state_q <= StDisable;
                 ==>
90             end else begin
91               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

103            unique case (state_q)
                      -1-  
104        
105              StDisable: begin
106                if (en_i) begin
                   -2-  
107                  state_d = StEnabling;
                     ==>
108                end
                   MISSING_ELSE
                   ==>
109              end
110        
111              StEnabling: begin
112                if (en_ref_sync) begin
                   -3-  
113                  state_d = StEnable;
                     ==>
114                end
                   MISSING_ELSE
                   ==>
115              end
116        
117              StEnable: begin
118                cnt_en = 1'b1;
119                if (!en_i) begin
                   -4-  
120                  state_d = StDisabling;
                     ==>
121                end
                   MISSING_ELSE
                   ==>
122              end
123        
124              StDisabling: begin
125                if (!en_ref_sync) begin
                   -5-  
126                  state_d = StDisable;
                     ==>
127                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T2,T3
StDisable	0	-	-	-	Covered	T1,T2,T3
StEnabling	-	1	-	-	Covered	T1,T3,T17
StEnabling	-	0	-	-	Covered	T1,T2,T3
StEnable	-	-	1	-	Covered	T1,T3,T17
StEnable	-	-	0	-	Covered	T1,T3,T17
StDisabling	-	-	-	1	Covered	T1,T3,T17
StDisabling	-	-	-	0	Covered	T1,T3,T17

183            if (!rst_ni) begin
               -1-  
184              cnt <= '0;
                 ==>
185              cnt_ovfl <= '0;
186            end else if (!cnt_en && |cnt) begin
                        -2-  
187              cnt <= '0;
                 ==>
188              cnt_ovfl <= '0;
189            end else if (valid_o) begin
                        -3-  
190              cnt <= '0;
                 ==>
191              cnt_ovfl <= '0;
192            end else if (cnt_ovfl) begin
                        -4-  
193              cnt <= '{default: '1};
                 ==>
194            end else if (cnt_en) begin
                        -5-  
195              {cnt_ovfl, cnt} <= cnt + 1'b1;
                 ==>
196            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T6
0	1	-	-	-	Covered	T1,T3,T17
0	0	1	-	-	Covered	T1,T3,T17
0	0	0	1	-	Covered	T3,T31,T9
0	0	0	0	1	Covered	T1,T3,T17
0	0	0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	73575126	0	0	0
RefCntVal_A	804	804	0	0
gen_timeout_assert.ClkRatios_A	804	804	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73575126	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

87                        always_ff @(posedge clk_i or negedge rst_ni) begin
88         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
89         1/1                state_q <= StDisable;
           Tests:       T4 T5 T6 
90                          end else begin
91         1/1                state_q <= state_d;
           Tests:       T4 T5 T6 
92                          end
93                        end
94                      
95                        // The following fsm sequence ensures that even if the source
96                        // side changes the enable too quickly, the measurement controls
97                        // remain consistent.
98                        logic cnt_en;
99                        always_comb begin
100        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
101        1/1              cnt_en = '0;
           Tests:       T1 T2 T3 
102                     
103        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
104                     
105                           StDisable: begin
106        1/1                  if (en_i) begin
           Tests:       T1 T2 T3 
107        1/1                    state_d = StEnabling;
           Tests:       T1 T2 T3 
108                             end
                        MISSING_ELSE
109                           end
110                     
111                           StEnabling: begin
112        1/1                  if (en_ref_sync) begin
           Tests:       T1 T2 T3 
113        1/1                    state_d = StEnable;
           Tests:       T1 T3 T17 
114                             end
                        MISSING_ELSE
115                           end
116                     
117                           StEnable: begin
118        1/1                  cnt_en = 1'b1;
           Tests:       T1 T3 T17 
119        1/1                  if (!en_i) begin
           Tests:       T1 T3 T17 
120        1/1                    state_d = StDisabling;
           Tests:       T1 T3 T17 
121                             end
                        MISSING_ELSE
122                           end
123                     
124                           StDisabling: begin
125        1/1                  if (!en_ref_sync) begin
           Tests:       T1 T3 T17 
126        1/1                    state_d = StDisable;
           Tests:       T1 T3 T17 
127                             end
                        MISSING_ELSE
128                           end
129                     
130                           //VCS coverage off
131                           // pragma coverage off
132                           default:;
133                           //VCS coverage on
134                           // pragma coverage on
135                     
136                         endcase // unique case (state_q)
137                       end
138                     
139                       //////////////////////////
140                       // Input Clock Logic
141                       //////////////////////////
142                     
143                       logic valid_ref;
144                       logic valid;
145                       // The valid pulse causes the count to reset and start counting again
146                       // for each reference cycle.
147                       // The count obtained during the last reference cycle is used
148                       // to measure how fast/slow the input clock is.
149                       prim_pulse_sync u_sync_ref (
150                         .clk_src_i(clk_ref_i),
151                         .rst_src_ni(rst_ref_ni),
152                         .src_pulse_i(ref_en),
153                         .clk_dst_i(clk_i),
154                         .rst_dst_ni(rst_ni),
155                         .dst_pulse_o(valid_ref)
156                       );
157                     
158                     
159                       if (RefCnt == 1) begin : gen_degenerate_case
160                         // if reference count is one, cnt_ref is always 0.
161                         // So there is no need to maintain a counter, and
162                         // valid just becomes valid_ref
163        1/1              assign valid = valid_ref;
           Tests:       T1 T3 T17 
164                       end else begin : gen_normal_case
165                         logic [RefCntWidth-1:0] cnt_ref;
166                         assign valid = valid_ref & (int'(cnt_ref) == RefCnt - 1);
167                         always_ff @(posedge clk_i or negedge rst_ni) begin
168                           if (!rst_ni) begin
169                             cnt_ref <= '0;
170                           end else if (!cnt_en && |cnt_ref) begin
171                             cnt_ref <= '0;
172                           end else if (cnt_en && valid) begin
173                             cnt_ref <= '0;
174                           end else if (cnt_en && valid_ref) begin
175                             cnt_ref <= cnt_ref + 1'b1;
176                           end
177                         end
178                       end
179                     
180                       logic cnt_ovfl;
181                       logic [CntWidth-1:0] cnt;
182                       always_ff @(posedge clk_i or negedge rst_ni) begin
183        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
184        1/1                cnt <= '0;
           Tests:       T4 T5 T6 
185        1/1                cnt_ovfl <= '0;
           Tests:       T4 T5 T6 
186        1/1              end else if (!cnt_en && |cnt) begin
           Tests:       T4 T5 T6 
187        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
188        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
189        1/1              end else if (valid_o) begin
           Tests:       T4 T5 T6 
190        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
191        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
192        1/1              end else if (cnt_ovfl) begin
           Tests:       T4 T5 T6 
193        1/1                cnt <= '{default: '1};
           Tests:       T31 T8 T12 
194        1/1              end else if (cnt_en) begin
           Tests:       T4 T5 T6 
195        1/1                {cnt_ovfl, cnt} <= cnt + 1'b1;
           Tests:       T1 T3 T17 
196                         end
                        MISSING_ELSE
197                       end
198                     
199        1/1            assign valid_o = valid & |cnt;
           Tests:       T1 T3 T17 
200        1/1            assign fast_o = valid_o & ((cnt > max_cnt) | cnt_ovfl);
           Tests:       T1 T2 T3 
201        1/1            assign slow_o = valid_o & (cnt < min_cnt);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T17

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T3,T17

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T8,T9
1	0	Covered	T1,T3,T17
1	1	Covered	T31,T8,T9

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T31,T8,T12
1	0	Covered	T31,T8,T9

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T17
1	1	Covered	T31,T12,T15

---

FSM Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T4,T5,T6
StDisabling	120	Covered	T1,T3,T17
StEnable	113	Covered	T1,T3,T17
StEnabling	107	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T2,T3
StDisabling->StDisable	126	Covered	T1,T3,T17
StEnable->StDisabling	120	Covered	T1,T3,T17
StEnabling->StEnable	113	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

88             if (!rst_ni) begin
               -1-  
89               state_q <= StDisable;
                 ==>
90             end else begin
91               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

103            unique case (state_q)
                      -1-  
104        
105              StDisable: begin
106                if (en_i) begin
                   -2-  
107                  state_d = StEnabling;
                     ==>
108                end
                   MISSING_ELSE
                   ==>
109              end
110        
111              StEnabling: begin
112                if (en_ref_sync) begin
                   -3-  
113                  state_d = StEnable;
                     ==>
114                end
                   MISSING_ELSE
                   ==>
115              end
116        
117              StEnable: begin
118                cnt_en = 1'b1;
119                if (!en_i) begin
                   -4-  
120                  state_d = StDisabling;
                     ==>
121                end
                   MISSING_ELSE
                   ==>
122              end
123        
124              StDisabling: begin
125                if (!en_ref_sync) begin
                   -5-  
126                  state_d = StDisable;
                     ==>
127                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T2,T3
StDisable	0	-	-	-	Covered	T1,T2,T3
StEnabling	-	1	-	-	Covered	T1,T3,T17
StEnabling	-	0	-	-	Covered	T1,T2,T3
StEnable	-	-	1	-	Covered	T1,T3,T17
StEnable	-	-	0	-	Covered	T1,T3,T17
StDisabling	-	-	-	1	Covered	T1,T3,T17
StDisabling	-	-	-	0	Covered	T1,T3,T17

183            if (!rst_ni) begin
               -1-  
184              cnt <= '0;
                 ==>
185              cnt_ovfl <= '0;
186            end else if (!cnt_en && |cnt) begin
                        -2-  
187              cnt <= '0;
                 ==>
188              cnt_ovfl <= '0;
189            end else if (valid_o) begin
                        -3-  
190              cnt <= '0;
                 ==>
191              cnt_ovfl <= '0;
192            end else if (cnt_ovfl) begin
                        -4-  
193              cnt <= '{default: '1};
                 ==>
194            end else if (cnt_en) begin
                        -5-  
195              {cnt_ovfl, cnt} <= cnt + 1'b1;
                 ==>
196            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T6
0	1	-	-	-	Covered	T1,T3,T17
0	0	1	-	-	Covered	T1,T3,T17
0	0	0	1	-	Covered	T31,T8,T12
0	0	0	0	1	Covered	T1,T3,T17
0	0	0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	35938955	0	0	0
RefCntVal_A	804	804	0	0
gen_timeout_assert.ClkRatios_A	804	804	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35938955	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

87                        always_ff @(posedge clk_i or negedge rst_ni) begin
88         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
89         1/1                state_q <= StDisable;
           Tests:       T4 T5 T6 
90                          end else begin
91         1/1                state_q <= state_d;
           Tests:       T4 T5 T6 
92                          end
93                        end
94                      
95                        // The following fsm sequence ensures that even if the source
96                        // side changes the enable too quickly, the measurement controls
97                        // remain consistent.
98                        logic cnt_en;
99                        always_comb begin
100        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
101        1/1              cnt_en = '0;
           Tests:       T1 T2 T3 
102                     
103        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
104                     
105                           StDisable: begin
106        1/1                  if (en_i) begin
           Tests:       T1 T2 T3 
107        1/1                    state_d = StEnabling;
           Tests:       T1 T2 T3 
108                             end
                        MISSING_ELSE
109                           end
110                     
111                           StEnabling: begin
112        1/1                  if (en_ref_sync) begin
           Tests:       T1 T2 T3 
113        1/1                    state_d = StEnable;
           Tests:       T1 T3 T17 
114                             end
                        MISSING_ELSE
115                           end
116                     
117                           StEnable: begin
118        1/1                  cnt_en = 1'b1;
           Tests:       T1 T3 T17 
119        1/1                  if (!en_i) begin
           Tests:       T1 T3 T17 
120        1/1                    state_d = StDisabling;
           Tests:       T1 T3 T17 
121                             end
                        MISSING_ELSE
122                           end
123                     
124                           StDisabling: begin
125        1/1                  if (!en_ref_sync) begin
           Tests:       T1 T3 T17 
126        1/1                    state_d = StDisable;
           Tests:       T1 T3 T17 
127                             end
                        MISSING_ELSE
128                           end
129                     
130                           //VCS coverage off
131                           // pragma coverage off
132                           default:;
133                           //VCS coverage on
134                           // pragma coverage on
135                     
136                         endcase // unique case (state_q)
137                       end
138                     
139                       //////////////////////////
140                       // Input Clock Logic
141                       //////////////////////////
142                     
143                       logic valid_ref;
144                       logic valid;
145                       // The valid pulse causes the count to reset and start counting again
146                       // for each reference cycle.
147                       // The count obtained during the last reference cycle is used
148                       // to measure how fast/slow the input clock is.
149                       prim_pulse_sync u_sync_ref (
150                         .clk_src_i(clk_ref_i),
151                         .rst_src_ni(rst_ref_ni),
152                         .src_pulse_i(ref_en),
153                         .clk_dst_i(clk_i),
154                         .rst_dst_ni(rst_ni),
155                         .dst_pulse_o(valid_ref)
156                       );
157                     
158                     
159                       if (RefCnt == 1) begin : gen_degenerate_case
160                         // if reference count is one, cnt_ref is always 0.
161                         // So there is no need to maintain a counter, and
162                         // valid just becomes valid_ref
163        1/1              assign valid = valid_ref;
           Tests:       T1 T3 T17 
164                       end else begin : gen_normal_case
165                         logic [RefCntWidth-1:0] cnt_ref;
166                         assign valid = valid_ref & (int'(cnt_ref) == RefCnt - 1);
167                         always_ff @(posedge clk_i or negedge rst_ni) begin
168                           if (!rst_ni) begin
169                             cnt_ref <= '0;
170                           end else if (!cnt_en && |cnt_ref) begin
171                             cnt_ref <= '0;
172                           end else if (cnt_en && valid) begin
173                             cnt_ref <= '0;
174                           end else if (cnt_en && valid_ref) begin
175                             cnt_ref <= cnt_ref + 1'b1;
176                           end
177                         end
178                       end
179                     
180                       logic cnt_ovfl;
181                       logic [CntWidth-1:0] cnt;
182                       always_ff @(posedge clk_i or negedge rst_ni) begin
183        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
184        1/1                cnt <= '0;
           Tests:       T4 T5 T6 
185        1/1                cnt_ovfl <= '0;
           Tests:       T4 T5 T6 
186        1/1              end else if (!cnt_en && |cnt) begin
           Tests:       T4 T5 T6 
187        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
188        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
189        1/1              end else if (valid_o) begin
           Tests:       T4 T5 T6 
190        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
191        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
192        1/1              end else if (cnt_ovfl) begin
           Tests:       T4 T5 T6 
193        1/1                cnt <= '{default: '1};
           Tests:       T9 T10 T11 
194        1/1              end else if (cnt_en) begin
           Tests:       T4 T5 T6 
195        1/1                {cnt_ovfl, cnt} <= cnt + 1'b1;
           Tests:       T1 T3 T17 
196                         end
                        MISSING_ELSE
197                       end
198                     
199        1/1            assign valid_o = valid & |cnt;
           Tests:       T1 T3 T17 
200        1/1            assign fast_o = valid_o & ((cnt > max_cnt) | cnt_ovfl);
           Tests:       T1 T2 T3 
201        1/1            assign slow_o = valid_o & (cnt < min_cnt);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T17

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T3,T17

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T31,T8
1	0	Covered	T1,T3,T17
1	1	Covered	T31,T8,T9

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T31,T8

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T17
1	1	Covered	T9,T13,T15

---

FSM Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T4,T5,T6
StDisabling	120	Covered	T1,T3,T17
StEnable	113	Covered	T1,T3,T17
StEnabling	107	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T2,T3
StDisabling->StDisable	126	Covered	T1,T3,T17
StEnable->StDisabling	120	Covered	T1,T3,T17
StEnabling->StEnable	113	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

88             if (!rst_ni) begin
               -1-  
89               state_q <= StDisable;
                 ==>
90             end else begin
91               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

103            unique case (state_q)
                      -1-  
104        
105              StDisable: begin
106                if (en_i) begin
                   -2-  
107                  state_d = StEnabling;
                     ==>
108                end
                   MISSING_ELSE
                   ==>
109              end
110        
111              StEnabling: begin
112                if (en_ref_sync) begin
                   -3-  
113                  state_d = StEnable;
                     ==>
114                end
                   MISSING_ELSE
                   ==>
115              end
116        
117              StEnable: begin
118                cnt_en = 1'b1;
119                if (!en_i) begin
                   -4-  
120                  state_d = StDisabling;
                     ==>
121                end
                   MISSING_ELSE
                   ==>
122              end
123        
124              StDisabling: begin
125                if (!en_ref_sync) begin
                   -5-  
126                  state_d = StDisable;
                     ==>
127                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T2,T3
StDisable	0	-	-	-	Covered	T1,T2,T3
StEnabling	-	1	-	-	Covered	T1,T3,T17
StEnabling	-	0	-	-	Covered	T1,T2,T3
StEnable	-	-	1	-	Covered	T1,T3,T17
StEnable	-	-	0	-	Covered	T1,T3,T17
StDisabling	-	-	-	1	Covered	T1,T3,T17
StDisabling	-	-	-	0	Covered	T1,T3,T17

183            if (!rst_ni) begin
               -1-  
184              cnt <= '0;
                 ==>
185              cnt_ovfl <= '0;
186            end else if (!cnt_en && |cnt) begin
                        -2-  
187              cnt <= '0;
                 ==>
188              cnt_ovfl <= '0;
189            end else if (valid_o) begin
                        -3-  
190              cnt <= '0;
                 ==>
191              cnt_ovfl <= '0;
192            end else if (cnt_ovfl) begin
                        -4-  
193              cnt <= '{default: '1};
                 ==>
194            end else if (cnt_en) begin
                        -5-  
195              {cnt_ovfl, cnt} <= cnt + 1'b1;
                 ==>
196            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T6
0	1	-	-	-	Covered	T1,T3,T17
0	0	1	-	-	Covered	T1,T3,T17
0	0	0	1	-	Covered	T9,T10,T11
0	0	0	0	1	Covered	T1,T3,T17
0	0	0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	17969019	0	0	0
RefCntVal_A	804	804	0	0
gen_timeout_assert.ClkRatios_A	804	804	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

87                        always_ff @(posedge clk_i or negedge rst_ni) begin
88         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
89         1/1                state_q <= StDisable;
           Tests:       T4 T5 T6 
90                          end else begin
91         1/1                state_q <= state_d;
           Tests:       T4 T5 T6 
92                          end
93                        end
94                      
95                        // The following fsm sequence ensures that even if the source
96                        // side changes the enable too quickly, the measurement controls
97                        // remain consistent.
98                        logic cnt_en;
99                        always_comb begin
100        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
101        1/1              cnt_en = '0;
           Tests:       T1 T2 T3 
102                     
103        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
104                     
105                           StDisable: begin
106        1/1                  if (en_i) begin
           Tests:       T1 T2 T3 
107        1/1                    state_d = StEnabling;
           Tests:       T1 T2 T3 
108                             end
                        MISSING_ELSE
109                           end
110                     
111                           StEnabling: begin
112        1/1                  if (en_ref_sync) begin
           Tests:       T1 T2 T3 
113        1/1                    state_d = StEnable;
           Tests:       T1 T3 T17 
114                             end
                        MISSING_ELSE
115                           end
116                     
117                           StEnable: begin
118        1/1                  cnt_en = 1'b1;
           Tests:       T1 T3 T17 
119        1/1                  if (!en_i) begin
           Tests:       T1 T3 T17 
120        1/1                    state_d = StDisabling;
           Tests:       T1 T3 T17 
121                             end
                        MISSING_ELSE
122                           end
123                     
124                           StDisabling: begin
125        1/1                  if (!en_ref_sync) begin
           Tests:       T1 T3 T17 
126        1/1                    state_d = StDisable;
           Tests:       T1 T3 T17 
127                             end
                        MISSING_ELSE
128                           end
129                     
130                           //VCS coverage off
131                           // pragma coverage off
132                           default:;
133                           //VCS coverage on
134                           // pragma coverage on
135                     
136                         endcase // unique case (state_q)
137                       end
138                     
139                       //////////////////////////
140                       // Input Clock Logic
141                       //////////////////////////
142                     
143                       logic valid_ref;
144                       logic valid;
145                       // The valid pulse causes the count to reset and start counting again
146                       // for each reference cycle.
147                       // The count obtained during the last reference cycle is used
148                       // to measure how fast/slow the input clock is.
149                       prim_pulse_sync u_sync_ref (
150                         .clk_src_i(clk_ref_i),
151                         .rst_src_ni(rst_ref_ni),
152                         .src_pulse_i(ref_en),
153                         .clk_dst_i(clk_i),
154                         .rst_dst_ni(rst_ni),
155                         .dst_pulse_o(valid_ref)
156                       );
157                     
158                     
159                       if (RefCnt == 1) begin : gen_degenerate_case
160                         // if reference count is one, cnt_ref is always 0.
161                         // So there is no need to maintain a counter, and
162                         // valid just becomes valid_ref
163        1/1              assign valid = valid_ref;
           Tests:       T1 T3 T17 
164                       end else begin : gen_normal_case
165                         logic [RefCntWidth-1:0] cnt_ref;
166                         assign valid = valid_ref & (int'(cnt_ref) == RefCnt - 1);
167                         always_ff @(posedge clk_i or negedge rst_ni) begin
168                           if (!rst_ni) begin
169                             cnt_ref <= '0;
170                           end else if (!cnt_en && |cnt_ref) begin
171                             cnt_ref <= '0;
172                           end else if (cnt_en && valid) begin
173                             cnt_ref <= '0;
174                           end else if (cnt_en && valid_ref) begin
175                             cnt_ref <= cnt_ref + 1'b1;
176                           end
177                         end
178                       end
179                     
180                       logic cnt_ovfl;
181                       logic [CntWidth-1:0] cnt;
182                       always_ff @(posedge clk_i or negedge rst_ni) begin
183        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
184        1/1                cnt <= '0;
           Tests:       T4 T5 T6 
185        1/1                cnt_ovfl <= '0;
           Tests:       T4 T5 T6 
186        1/1              end else if (!cnt_en && |cnt) begin
           Tests:       T4 T5 T6 
187        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
188        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
189        1/1              end else if (valid_o) begin
           Tests:       T4 T5 T6 
190        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
191        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
192        1/1              end else if (cnt_ovfl) begin
           Tests:       T4 T5 T6 
193        1/1                cnt <= '{default: '1};
           Tests:       T31 T8 T10 
194        1/1              end else if (cnt_en) begin
           Tests:       T4 T5 T6 
195        1/1                {cnt_ovfl, cnt} <= cnt + 1'b1;
           Tests:       T1 T3 T17 
196                         end
                        MISSING_ELSE
197                       end
198                     
199        1/1            assign valid_o = valid & |cnt;
           Tests:       T1 T3 T17 
200        1/1            assign fast_o = valid_o & ((cnt > max_cnt) | cnt_ovfl);
           Tests:       T1 T2 T3 
201        1/1            assign slow_o = valid_o & (cnt < min_cnt);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T17

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T3,T17

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T8,T10
1	0	Covered	T1,T3,T17
1	1	Covered	T31,T8,T10

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T31,T8,T10
1	0	Covered	T31,T8,T10

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T17
1	1	Covered	T31,T10,T15

---

FSM Coverage for Instance : tb.dut.u_main_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T4,T5,T6
StDisabling	120	Covered	T1,T3,T17
StEnable	113	Covered	T1,T3,T17
StEnabling	107	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T2,T3
StDisabling->StDisable	126	Covered	T1,T3,T17
StEnable->StDisabling	120	Covered	T1,T3,T17
StEnabling->StEnable	113	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

88             if (!rst_ni) begin
               -1-  
89               state_q <= StDisable;
                 ==>
90             end else begin
91               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

103            unique case (state_q)
                      -1-  
104        
105              StDisable: begin
106                if (en_i) begin
                   -2-  
107                  state_d = StEnabling;
                     ==>
108                end
                   MISSING_ELSE
                   ==>
109              end
110        
111              StEnabling: begin
112                if (en_ref_sync) begin
                   -3-  
113                  state_d = StEnable;
                     ==>
114                end
                   MISSING_ELSE
                   ==>
115              end
116        
117              StEnable: begin
118                cnt_en = 1'b1;
119                if (!en_i) begin
                   -4-  
120                  state_d = StDisabling;
                     ==>
121                end
                   MISSING_ELSE
                   ==>
122              end
123        
124              StDisabling: begin
125                if (!en_ref_sync) begin
                   -5-  
126                  state_d = StDisable;
                     ==>
127                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T2,T3
StDisable	0	-	-	-	Covered	T1,T2,T3
StEnabling	-	1	-	-	Covered	T1,T3,T17
StEnabling	-	0	-	-	Covered	T1,T2,T3
StEnable	-	-	1	-	Covered	T1,T3,T17
StEnable	-	-	0	-	Covered	T1,T3,T17
StDisabling	-	-	-	1	Covered	T1,T3,T17
StDisabling	-	-	-	0	Covered	T1,T3,T17

183            if (!rst_ni) begin
               -1-  
184              cnt <= '0;
                 ==>
185              cnt_ovfl <= '0;
186            end else if (!cnt_en && |cnt) begin
                        -2-  
187              cnt <= '0;
                 ==>
188              cnt_ovfl <= '0;
189            end else if (valid_o) begin
                        -3-  
190              cnt <= '0;
                 ==>
191              cnt_ovfl <= '0;
192            end else if (cnt_ovfl) begin
                        -4-  
193              cnt <= '{default: '1};
                 ==>
194            end else if (cnt_en) begin
                        -5-  
195              {cnt_ovfl, cnt} <= cnt + 1'b1;
                 ==>
196            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T6
0	1	-	-	-	Covered	T1,T3,T17
0	0	1	-	-	Covered	T1,T3,T17
0	0	0	1	-	Covered	T31,T8,T10
0	0	0	0	1	Covered	T1,T3,T17
0	0	0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	81423641	0	0	0
RefCntVal_A	804	804	0	0
gen_timeout_assert.ClkRatios_A	804	804	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	88	3	3	100.00
ALWAYS	100	12	12	100.00
CONT_ASSIGN	163	1	1	100.00
ALWAYS	183	13	13	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

87                        always_ff @(posedge clk_i or negedge rst_ni) begin
88         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
89         1/1                state_q <= StDisable;
           Tests:       T4 T5 T6 
90                          end else begin
91         1/1                state_q <= state_d;
           Tests:       T4 T5 T6 
92                          end
93                        end
94                      
95                        // The following fsm sequence ensures that even if the source
96                        // side changes the enable too quickly, the measurement controls
97                        // remain consistent.
98                        logic cnt_en;
99                        always_comb begin
100        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
101        1/1              cnt_en = '0;
           Tests:       T1 T2 T3 
102                     
103        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
104                     
105                           StDisable: begin
106        1/1                  if (en_i) begin
           Tests:       T1 T2 T3 
107        1/1                    state_d = StEnabling;
           Tests:       T1 T2 T3 
108                             end
                        MISSING_ELSE
109                           end
110                     
111                           StEnabling: begin
112        1/1                  if (en_ref_sync) begin
           Tests:       T1 T2 T3 
113        1/1                    state_d = StEnable;
           Tests:       T1 T3 T17 
114                             end
                        MISSING_ELSE
115                           end
116                     
117                           StEnable: begin
118        1/1                  cnt_en = 1'b1;
           Tests:       T1 T3 T17 
119        1/1                  if (!en_i) begin
           Tests:       T1 T3 T17 
120        1/1                    state_d = StDisabling;
           Tests:       T1 T3 T17 
121                             end
                        MISSING_ELSE
122                           end
123                     
124                           StDisabling: begin
125        1/1                  if (!en_ref_sync) begin
           Tests:       T1 T3 T17 
126        1/1                    state_d = StDisable;
           Tests:       T1 T3 T17 
127                             end
                        MISSING_ELSE
128                           end
129                     
130                           //VCS coverage off
131                           // pragma coverage off
132                           default:;
133                           //VCS coverage on
134                           // pragma coverage on
135                     
136                         endcase // unique case (state_q)
137                       end
138                     
139                       //////////////////////////
140                       // Input Clock Logic
141                       //////////////////////////
142                     
143                       logic valid_ref;
144                       logic valid;
145                       // The valid pulse causes the count to reset and start counting again
146                       // for each reference cycle.
147                       // The count obtained during the last reference cycle is used
148                       // to measure how fast/slow the input clock is.
149                       prim_pulse_sync u_sync_ref (
150                         .clk_src_i(clk_ref_i),
151                         .rst_src_ni(rst_ref_ni),
152                         .src_pulse_i(ref_en),
153                         .clk_dst_i(clk_i),
154                         .rst_dst_ni(rst_ni),
155                         .dst_pulse_o(valid_ref)
156                       );
157                     
158                     
159                       if (RefCnt == 1) begin : gen_degenerate_case
160                         // if reference count is one, cnt_ref is always 0.
161                         // So there is no need to maintain a counter, and
162                         // valid just becomes valid_ref
163        1/1              assign valid = valid_ref;
           Tests:       T1 T3 T17 
164                       end else begin : gen_normal_case
165                         logic [RefCntWidth-1:0] cnt_ref;
166                         assign valid = valid_ref & (int'(cnt_ref) == RefCnt - 1);
167                         always_ff @(posedge clk_i or negedge rst_ni) begin
168                           if (!rst_ni) begin
169                             cnt_ref <= '0;
170                           end else if (!cnt_en && |cnt_ref) begin
171                             cnt_ref <= '0;
172                           end else if (cnt_en && valid) begin
173                             cnt_ref <= '0;
174                           end else if (cnt_en && valid_ref) begin
175                             cnt_ref <= cnt_ref + 1'b1;
176                           end
177                         end
178                       end
179                     
180                       logic cnt_ovfl;
181                       logic [CntWidth-1:0] cnt;
182                       always_ff @(posedge clk_i or negedge rst_ni) begin
183        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
184        1/1                cnt <= '0;
           Tests:       T4 T5 T6 
185        1/1                cnt_ovfl <= '0;
           Tests:       T4 T5 T6 
186        1/1              end else if (!cnt_en && |cnt) begin
           Tests:       T4 T5 T6 
187        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
188        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
189        1/1              end else if (valid_o) begin
           Tests:       T4 T5 T6 
190        1/1                cnt <= '0;
           Tests:       T1 T3 T17 
191        1/1                cnt_ovfl <= '0;
           Tests:       T1 T3 T17 
192        1/1              end else if (cnt_ovfl) begin
           Tests:       T4 T5 T6 
193        1/1                cnt <= '{default: '1};
           Tests:       T1 T31 T8 
194        1/1              end else if (cnt_en) begin
           Tests:       T4 T5 T6 
195        1/1                {cnt_ovfl, cnt} <= cnt + 1'b1;
           Tests:       T1 T3 T17 
196                         end
                        MISSING_ELSE
197                       end
198                     
199        1/1            assign valid_o = valid & |cnt;
           Tests:       T1 T3 T17 
200        1/1            assign fast_o = valid_o & ((cnt > max_cnt) | cnt_ovfl);
           Tests:       T1 T2 T3 
201        1/1            assign slow_o = valid_o & (cnt < min_cnt);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T17

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T3,T17

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T8
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T31,T8

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T31,T8
1	0	Covered	T1,T31,T8

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T17
1	1	Covered	T31,T13,T15

---

FSM Coverage for Instance : tb.dut.u_usb_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Covered	T4,T5,T6
StDisabling	120	Covered	T1,T3,T17
StEnable	113	Covered	T1,T3,T17
StEnabling	107	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Covered	T1,T2,T3
StDisabling->StDisable	126	Covered	T1,T3,T17
StEnable->StDisabling	120	Covered	T1,T3,T17
StEnabling->StEnable	113	Covered	T1,T3,T17

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	88	2	2	100.00
CASE	103	8	8	100.00
IF	183	6	6	100.00

88             if (!rst_ni) begin
               -1-  
89               state_q <= StDisable;
                 ==>
90             end else begin
91               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

103            unique case (state_q)
                      -1-  
104        
105              StDisable: begin
106                if (en_i) begin
                   -2-  
107                  state_d = StEnabling;
                     ==>
108                end
                   MISSING_ELSE
                   ==>
109              end
110        
111              StEnabling: begin
112                if (en_ref_sync) begin
                   -3-  
113                  state_d = StEnable;
                     ==>
114                end
                   MISSING_ELSE
                   ==>
115              end
116        
117              StEnable: begin
118                cnt_en = 1'b1;
119                if (!en_i) begin
                   -4-  
120                  state_d = StDisabling;
                     ==>
121                end
                   MISSING_ELSE
                   ==>
122              end
123        
124              StDisabling: begin
125                if (!en_ref_sync) begin
                   -5-  
126                  state_d = StDisable;
                     ==>
127                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Covered	T1,T2,T3
StDisable	0	-	-	-	Covered	T1,T2,T3
StEnabling	-	1	-	-	Covered	T1,T3,T17
StEnabling	-	0	-	-	Covered	T1,T2,T3
StEnable	-	-	1	-	Covered	T1,T3,T17
StEnable	-	-	0	-	Covered	T1,T3,T17
StDisabling	-	-	-	1	Covered	T1,T3,T17
StDisabling	-	-	-	0	Covered	T1,T3,T17

183            if (!rst_ni) begin
               -1-  
184              cnt <= '0;
                 ==>
185              cnt_ovfl <= '0;
186            end else if (!cnt_en && |cnt) begin
                        -2-  
187              cnt <= '0;
                 ==>
188              cnt_ovfl <= '0;
189            end else if (valid_o) begin
                        -3-  
190              cnt <= '0;
                 ==>
191              cnt_ovfl <= '0;
192            end else if (cnt_ovfl) begin
                        -4-  
193              cnt <= '{default: '1};
                 ==>
194            end else if (cnt_en) begin
                        -5-  
195              {cnt_ovfl, cnt} <= cnt + 1'b1;
                 ==>
196            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T5,T6
0	1	-	-	-	Covered	T1,T3,T17
0	0	1	-	-	Covered	T1,T3,T17
0	0	0	1	-	Covered	T1,T31,T8
0	0	0	0	1	Covered	T1,T3,T17
0	0	0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxWidth_A	39061206	0	0	0
RefCntVal_A	804	804	0	0
gen_timeout_assert.ClkRatios_A	804	804	0	0

MaxWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39061206	0	0	0

RefCntVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_timeout_assert.ClkRatios_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	804	804	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0