Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	117559521	443	0	0
StatusRise_A	117559521	443	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117559521	443	0	0
T4	3984	5	0	0
T5	5184	0	0	0
T6	5055	0	0	0
T20	0	10	0	0
T24	4395	0	0	0
T25	6075	0	0	0
T26	5802	0	0	0
T27	6660	0	0	0
T28	4551	0	0	0
T29	6978	0	0	0
T30	8259	0	0	0
T36	0	12	0	0
T42	0	5	0	0
T76	0	8	0	0
T198	0	4	0	0
T199	0	11	0	0
T200	0	14	0	0
T201	0	4	0	0
T202	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117559521	443	0	0
T4	3984	5	0	0
T5	5184	0	0	0
T6	5055	0	0	0
T20	0	10	0	0
T24	4395	0	0	0
T25	6075	0	0	0
T26	5802	0	0	0
T27	6660	0	0	0
T28	4551	0	0	0
T29	6978	0	0	0
T30	8259	0	0	0
T36	0	12	0	0
T42	0	5	0	0
T76	0	8	0	0
T198	0	4	0	0
T199	0	11	0	0
T200	0	14	0	0
T201	0	4	0	0
T202	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39186507	156	0	0
StatusRise_A	39186507	156	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	156	0	0
T4	1328	2	0	0
T5	1728	0	0	0
T6	1685	0	0	0
T20	0	3	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	5	0	0
T42	0	2	0	0
T76	0	2	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	2	0	0
T202	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	156	0	0
T4	1328	2	0	0
T5	1728	0	0	0
T6	1685	0	0	0
T20	0	3	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	5	0	0
T42	0	2	0	0
T76	0	2	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	2	0	0
T202	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39186507	148	0	0
StatusRise_A	39186507	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	148	0	0
T4	1328	2	0	0
T5	1728	0	0	0
T6	1685	0	0	0
T20	0	5	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	148	0	0
T4	1328	2	0	0
T5	1728	0	0	0
T6	1685	0	0	0
T20	0	5	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39186507	139	0	0
StatusRise_A	39186507	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	139	0	0
T4	1328	1	0	0
T5	1728	0	0	0
T6	1685	0	0	0
T20	0	2	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T76	0	3	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	4	0	0
T201	0	1	0	0
T202	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39186507	139	0	0
T4	1328	1	0	0
T5	1728	0	0	0
T6	1685	0	0	0
T20	0	2	0	0
T24	1465	0	0	0
T25	2025	0	0	0
T26	1934	0	0	0
T27	2220	0	0	0
T28	1517	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T76	0	3	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	4	0	0
T201	0	1	0	0
T202	0	3	0	0