Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	857568496	32852	0	0
CgEnOn_A	857568496	23624	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857568496	32852	0	0
T4	14298	21	0	0
T5	18606	50	0	0
T6	72784	7	0	0
T20	0	25	0	0
T24	17816	3	0	0
T25	22880	3	0	0
T26	84154	3	0	0
T27	47900	11	0	0
T28	65452	7	0	0
T29	26602	3	0	0
T30	31730	3	0	0
T36	0	15	0	0
T42	0	10	0	0
T72	0	1	0	0
T76	0	17	0	0
T77	0	1	0	0
T198	0	5	0	0
T199	0	20	0	0
T200	0	25	0	0
T201	0	5	0	0
T202	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	857568496	23624	0	0
T4	14298	18	0	0
T5	18606	47	0	0
T6	72784	4	0	0
T18	0	11	0	0
T19	0	4	0	0
T20	0	40	0	0
T24	17816	0	0	0
T25	22880	0	0	0
T26	84154	0	0	0
T27	47900	8	0	0
T28	65452	4	0	0
T29	26602	0	0	0
T30	31730	0	0	0
T36	0	15	0	0
T42	0	10	0	0
T72	0	4	0	0
T74	0	24	0	0
T76	0	26	0	0
T77	0	4	0	0
T78	0	2	0	0
T135	0	3	0	0
T198	0	5	0	0
T199	0	20	0	0
T200	0	25	0	0
T201	0	5	0	0
T202	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	35938955	168	0	0
CgEnOn_A	35938955	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35938955	168	0	0
T4	619	2	0	0
T5	777	0	0	0
T6	3225	0	0	0
T20	0	5	0	0
T24	1169	0	0	0
T25	1038	0	0	0
T26	3859	0	0	0
T27	2113	0	0	0
T28	2887	0	0	0
T29	1270	0	0	0
T30	1568	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35938955	168	0	0
T4	619	2	0	0
T5	777	0	0	0
T6	3225	0	0	0
T20	0	5	0	0
T24	1169	0	0	0
T25	1038	0	0	0
T26	3859	0	0	0
T27	2113	0	0	0
T28	2887	0	0	0
T29	1270	0	0	0
T30	1568	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17969019	168	0	0
CgEnOn_A	17969019	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	168	0	0
T4	310	2	0	0
T5	389	0	0	0
T6	1612	0	0	0
T20	0	5	0	0
T24	584	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1056	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	782	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	168	0	0
T4	310	2	0	0
T5	389	0	0	0
T6	1612	0	0	0
T20	0	5	0	0
T24	584	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1056	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	782	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17969019	168	0	0
CgEnOn_A	17969019	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	168	0	0
T4	310	2	0	0
T5	389	0	0	0
T6	1612	0	0	0
T20	0	5	0	0
T24	584	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1056	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	782	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	168	0	0
T4	310	2	0	0
T5	389	0	0	0
T6	1612	0	0	0
T20	0	5	0	0
T24	584	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1056	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	782	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17969019	168	0	0
CgEnOn_A	17969019	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	168	0	0
T4	310	2	0	0
T5	389	0	0	0
T6	1612	0	0	0
T20	0	5	0	0
T24	584	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1056	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	782	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	168	0	0
T4	310	2	0	0
T5	389	0	0	0
T6	1612	0	0	0
T20	0	5	0	0
T24	584	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1056	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	782	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	73575126	168	0	0
CgEnOn_A	73575126	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73575126	168	0	0
T4	1291	2	0	0
T5	1675	0	0	0
T6	6474	0	0	0
T20	0	5	0	0
T24	1421	0	0	0
T25	2025	0	0	0
T26	7429	0	0	0
T27	4264	0	0	0
T28	5827	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73575126	152	0	0
T4	1291	2	0	0
T5	1675	0	0	0
T6	6474	0	0	0
T20	0	5	0	0
T24	1421	0	0	0
T25	2025	0	0	0
T26	7429	0	0	0
T27	4264	0	0	0
T28	5827	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T36	0	3	0	0
T42	0	2	0	0
T76	0	3	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81423641	161	0	0
CgEnOn_A	81423641	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	161	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	0	0	0
T20	0	3	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	0	0	0
T28	6070	0	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T36	0	5	0	0
T42	0	2	0	0
T76	0	2	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	2	0	0
T202	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	157	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	0	0	0
T20	0	3	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	0	0	0
T28	6070	0	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T36	0	5	0	0
T42	0	2	0	0
T76	0	2	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	2	0	0
T202	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81423641	161	0	0
CgEnOn_A	81423641	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	161	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	0	0	0
T20	0	3	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	0	0	0
T28	6070	0	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T36	0	5	0	0
T42	0	2	0	0
T76	0	2	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	2	0	0
T202	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	157	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	0	0	0
T20	0	3	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	0	0	0
T28	6070	0	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T36	0	5	0	0
T42	0	2	0	0
T76	0	2	0	0
T198	0	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T201	0	2	0	0
T202	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39061206	149	0	0
CgEnOn_A	39061206	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39061206	149	0	0
T4	605	1	0	0
T5	838	0	0	0
T6	3237	0	0	0
T20	0	2	0	0
T24	710	0	0	0
T25	1012	0	0	0
T26	3714	0	0	0
T27	2132	0	0	0
T28	2914	0	0	0
T29	1163	0	0	0
T30	1376	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T76	0	3	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	4	0	0
T201	0	1	0	0
T202	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39061206	142	0	0
T4	605	1	0	0
T5	838	0	0	0
T6	3237	0	0	0
T20	0	2	0	0
T24	710	0	0	0
T25	1012	0	0	0
T26	3714	0	0	0
T27	2132	0	0	0
T28	2914	0	0	0
T29	1163	0	0	0
T30	1376	0	0	0
T36	0	4	0	0
T42	0	1	0	0
T76	0	3	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	4	0	0
T201	0	1	0	0
T202	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17969019	5388	0	0
CgEnOn_A	17969019	3101	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	5388	0	0
T4	310	3	0	0
T5	389	17	0	0
T6	1612	2	0	0
T24	584	1	0	0
T25	519	1	0	0
T26	1929	1	0	0
T27	1056	1	0	0
T28	1444	1	0	0
T29	635	1	0	0
T30	782	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17969019	3101	0	0
T4	310	2	0	0
T5	389	16	0	0
T6	1612	1	0	0
T18	0	3	0	0
T19	0	1	0	0
T20	0	5	0	0
T24	584	0	0	0
T25	519	0	0	0
T26	1929	0	0	0
T27	1056	0	0	0
T28	1444	0	0	0
T29	635	0	0	0
T30	782	0	0	0
T72	0	1	0	0
T74	0	8	0	0
T76	0	3	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	35938955	5420	0	0
CgEnOn_A	35938955	3133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35938955	5420	0	0
T4	619	3	0	0
T5	777	16	0	0
T6	3225	2	0	0
T24	1169	1	0	0
T25	1038	1	0	0
T26	3859	1	0	0
T27	2113	1	0	0
T28	2887	1	0	0
T29	1270	1	0	0
T30	1568	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35938955	3133	0	0
T4	619	2	0	0
T5	777	15	0	0
T6	3225	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	5	0	0
T24	1169	0	0	0
T25	1038	0	0	0
T26	3859	0	0	0
T27	2113	0	0	0
T28	2887	0	0	0
T29	1270	0	0	0
T30	1568	0	0	0
T72	0	1	0	0
T74	0	8	0	0
T76	0	3	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	73575126	5405	0	0
CgEnOn_A	73575126	3102	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73575126	5405	0	0
T4	1291	3	0	0
T5	1675	17	0	0
T6	6474	2	0	0
T24	1421	1	0	0
T25	2025	1	0	0
T26	7429	1	0	0
T27	4264	1	0	0
T28	5827	1	0	0
T29	2326	1	0	0
T30	2753	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73575126	3102	0	0
T4	1291	2	0	0
T5	1675	16	0	0
T6	6474	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	5	0	0
T24	1421	0	0	0
T25	2025	0	0	0
T26	7429	0	0	0
T27	4264	0	0	0
T28	5827	0	0	0
T29	2326	0	0	0
T30	2753	0	0	0
T72	0	1	0	0
T74	0	8	0	0
T76	0	3	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39061206	5400	0	0
CgEnOn_A	39061206	3096	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39061206	5400	0	0
T4	605	2	0	0
T5	838	15	0	0
T6	3237	2	0	0
T24	710	1	0	0
T25	1012	1	0	0
T26	3714	1	0	0
T27	2132	1	0	0
T28	2914	1	0	0
T29	1163	1	0	0
T30	1376	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39061206	3096	0	0
T4	605	1	0	0
T5	838	14	0	0
T6	3237	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T20	0	2	0	0
T24	710	0	0	0
T25	1012	0	0	0
T26	3714	0	0	0
T27	2132	0	0	0
T28	2914	0	0	0
T29	1163	0	0	0
T30	1376	0	0	0
T72	0	1	0	0
T74	0	8	0	0
T76	0	3	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Covered	T6,T27,T28
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81423641	2473	0	0
CgEnOn_A	81423641	2469	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2473	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	8	0	0
T28	6070	4	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T135	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2469	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	8	0	0
T28	6070	4	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T135	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Covered	T6,T27,T28
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81423641	2505	0	0
CgEnOn_A	81423641	2501	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2505	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	7	0	0
T28	6070	3	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T135	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2501	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	7	0	0
T28	6070	3	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T135	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Covered	T6,T27,T28
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81423641	2509	0	0
CgEnOn_A	81423641	2505	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2509	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T20	0	3	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	10	0	0
T28	6070	2	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T135	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2505	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T20	0	3	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	10	0	0
T28	6070	2	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T135	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T76,T98
1	0	Covered	T6,T27,T28
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81423641	2441	0	0
CgEnOn_A	81423641	2437	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2441	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	4	0	0
T28	6070	5	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	3	0	0
T135	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81423641	2437	0	0
T4	1338	2	0	0
T5	1745	0	0	0
T6	6744	1	0	0
T19	0	1	0	0
T24	1480	0	0	0
T25	2109	0	0	0
T26	7739	0	0	0
T27	4443	4	0	0
T28	6070	5	0	0
T29	2424	0	0	0
T30	2868	0	0	0
T72	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	3	0	0
T135	0	5	0	0