Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1009
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T802 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.2915438283 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:14 AM UTC 24 22181895 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.1662801960 Oct 12 12:56:12 AM UTC 24 Oct 12 12:56:14 AM UTC 24 14925020 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.1537573997 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:14 AM UTC 24 122034117 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.1948694035 Oct 12 12:56:12 AM UTC 24 Oct 12 12:56:14 AM UTC 24 78576009 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.1105388276 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:15 AM UTC 24 370547442 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.406293683 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:15 AM UTC 24 193421849 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.4213162148 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:16 AM UTC 24 733718751 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.40759904 Oct 12 12:56:10 AM UTC 24 Oct 12 12:56:16 AM UTC 24 1030800485 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.2666451051 Oct 12 12:56:00 AM UTC 24 Oct 12 12:56:17 AM UTC 24 938605195 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.1209159124 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:19 AM UTC 24 795617967 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.2408872701 Oct 12 12:55:15 AM UTC 24 Oct 12 12:56:19 AM UTC 24 4530963442 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.1876866225 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:20 AM UTC 24 979295782 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.1713808967 Oct 12 12:56:12 AM UTC 24 Oct 12 12:56:20 AM UTC 24 915450066 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.4288667290 Oct 12 12:56:12 AM UTC 24 Oct 12 12:56:23 AM UTC 24 1942481691 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.4236782924 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 12413339 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1852728096 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 27227741 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1337817241 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 20206640 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2000730049 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 24964867 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.2261639015 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 42389195 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.4230117692 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 73949992 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.3044400889 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 20776055 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.2855487830 Oct 12 12:55:16 AM UTC 24 Oct 12 12:56:28 AM UTC 24 12009995772 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.504000471 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:28 AM UTC 24 28290470 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.275852174 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:29 AM UTC 24 263051953 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.3422659293 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:28 AM UTC 24 27295548 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.995636761 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:29 AM UTC 24 13132107 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3611543968 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:29 AM UTC 24 10604794 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2288547527 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:29 AM UTC 24 14523584 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.1302826767 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:29 AM UTC 24 275236491 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.3489449647 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:29 AM UTC 24 77316291 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.499804315 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:29 AM UTC 24 80896976 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.2534297874 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:29 AM UTC 24 17003430 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.2857772316 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:29 AM UTC 24 37364339 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.1827897417 Oct 12 12:55:37 AM UTC 24 Oct 12 12:56:29 AM UTC 24 3210994881 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.598229741 Oct 12 12:56:00 AM UTC 24 Oct 12 12:56:32 AM UTC 24 8146287780 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.3758302790 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:33 AM UTC 24 1114426384 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.3938711608 Oct 12 12:54:38 AM UTC 24 Oct 12 12:56:35 AM UTC 24 17894371508 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.3652741369 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:35 AM UTC 24 1186225454 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.1717606704 Oct 12 12:55:29 AM UTC 24 Oct 12 12:56:38 AM UTC 24 8126846485 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.881475226 Oct 12 12:55:47 AM UTC 24 Oct 12 12:56:38 AM UTC 24 4637696718 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.1986383933 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:39 AM UTC 24 2908497852 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.1927200898 Oct 12 12:56:11 AM UTC 24 Oct 12 12:56:41 AM UTC 24 7448604603 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.2265624974 Oct 12 12:56:26 AM UTC 24 Oct 12 12:56:41 AM UTC 24 1636539799 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.2557147915 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:43 AM UTC 24 3205737329 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.3367757033 Oct 12 12:55:47 AM UTC 24 Oct 12 12:56:44 AM UTC 24 7530064091 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.2768046182 Oct 12 12:55:47 AM UTC 24 Oct 12 12:56:45 AM UTC 24 3144528959 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.1129955814 Oct 12 12:55:37 AM UTC 24 Oct 12 12:57:02 AM UTC 24 21208387840 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.694714206 Oct 12 12:56:00 AM UTC 24 Oct 12 12:57:08 AM UTC 24 4860342861 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.2457739280 Oct 12 12:56:26 AM UTC 24 Oct 12 12:57:11 AM UTC 24 7259069415 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3170642510 Oct 12 12:56:26 AM UTC 24 Oct 12 12:57:13 AM UTC 24 5954787757 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.45195398 Oct 12 12:56:11 AM UTC 24 Oct 12 12:57:17 AM UTC 24 6630359377 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.271305205 Oct 12 12:56:00 AM UTC 24 Oct 12 12:57:22 AM UTC 24 11198868288 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.796637056 Oct 12 12:56:27 AM UTC 24 Oct 12 12:57:32 AM UTC 24 3338940264 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.2145105791 Oct 12 12:55:21 AM UTC 24 Oct 12 12:57:58 AM UTC 24 26685748765 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.777754499 Oct 12 12:34:33 AM UTC 24 Oct 12 12:34:36 AM UTC 24 93636781 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4208595992 Oct 12 12:34:35 AM UTC 24 Oct 12 12:34:39 AM UTC 24 99703956 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.1618848056 Oct 12 12:34:36 AM UTC 24 Oct 12 12:34:39 AM UTC 24 77331366 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1092262003 Oct 12 12:34:37 AM UTC 24 Oct 12 12:34:42 AM UTC 24 128286274 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.1454908538 Oct 12 12:34:40 AM UTC 24 Oct 12 12:34:42 AM UTC 24 19566547 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.554514127 Oct 12 12:34:40 AM UTC 24 Oct 12 12:34:42 AM UTC 24 16145206 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.493069070 Oct 12 12:34:42 AM UTC 24 Oct 12 12:34:44 AM UTC 24 16203370 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3428888309 Oct 12 12:34:45 AM UTC 24 Oct 12 12:34:47 AM UTC 24 29942120 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4167024558 Oct 12 12:34:45 AM UTC 24 Oct 12 12:34:48 AM UTC 24 55260233 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.4240021778 Oct 12 12:34:43 AM UTC 24 Oct 12 12:34:50 AM UTC 24 624253248 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3758436468 Oct 12 12:34:48 AM UTC 24 Oct 12 12:34:52 AM UTC 24 91367627 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.869817895 Oct 12 12:34:48 AM UTC 24 Oct 12 12:34:52 AM UTC 24 47834645 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3275019521 Oct 12 12:34:48 AM UTC 24 Oct 12 12:34:53 AM UTC 24 231214961 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.2850040235 Oct 12 12:34:53 AM UTC 24 Oct 12 12:34:55 AM UTC 24 58337474 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3678129693 Oct 12 12:34:53 AM UTC 24 Oct 12 12:34:55 AM UTC 24 35303526 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.1114038793 Oct 12 12:34:54 AM UTC 24 Oct 12 12:34:56 AM UTC 24 29533013 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2123965598 Oct 12 12:34:50 AM UTC 24 Oct 12 12:34:57 AM UTC 24 217965386 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3737169452 Oct 12 12:34:43 AM UTC 24 Oct 12 12:34:58 AM UTC 24 418927218 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1299359743 Oct 12 12:34:56 AM UTC 24 Oct 12 12:34:59 AM UTC 24 75981852 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1812994654 Oct 12 12:34:57 AM UTC 24 Oct 12 12:35:00 AM UTC 24 53638199 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3818452400 Oct 12 12:34:57 AM UTC 24 Oct 12 12:35:00 AM UTC 24 100372776 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1421067069 Oct 12 12:34:59 AM UTC 24 Oct 12 12:35:04 AM UTC 24 164675039 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1689340121 Oct 12 12:35:00 AM UTC 24 Oct 12 12:35:04 AM UTC 24 87632755 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.1726978276 Oct 12 12:35:00 AM UTC 24 Oct 12 12:35:05 AM UTC 24 100708665 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1895916313 Oct 12 12:35:00 AM UTC 24 Oct 12 12:35:06 AM UTC 24 120866631 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1625792742 Oct 12 12:34:56 AM UTC 24 Oct 12 12:35:06 AM UTC 24 753853967 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.808780972 Oct 12 12:35:04 AM UTC 24 Oct 12 12:35:07 AM UTC 24 37207741 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.544325922 Oct 12 12:35:05 AM UTC 24 Oct 12 12:35:08 AM UTC 24 49635126 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.3844383181 Oct 12 12:35:10 AM UTC 24 Oct 12 12:35:12 AM UTC 24 50908913 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.740826354 Oct 12 12:35:10 AM UTC 24 Oct 12 12:35:13 AM UTC 24 90675513 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.461868919 Oct 12 12:35:11 AM UTC 24 Oct 12 12:35:14 AM UTC 24 76205631 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3582808203 Oct 12 12:35:11 AM UTC 24 Oct 12 12:35:14 AM UTC 24 41593201 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3353369279 Oct 12 12:35:11 AM UTC 24 Oct 12 12:35:15 AM UTC 24 100523308 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.2354795233 Oct 12 12:35:14 AM UTC 24 Oct 12 12:35:16 AM UTC 24 29404897 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.967590491 Oct 12 12:35:14 AM UTC 24 Oct 12 12:35:17 AM UTC 24 26216289 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1094288610 Oct 12 12:35:13 AM UTC 24 Oct 12 12:35:17 AM UTC 24 99342156 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.1393138054 Oct 12 12:35:13 AM UTC 24 Oct 12 12:35:18 AM UTC 24 109395132 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.1095239270 Oct 12 12:35:15 AM UTC 24 Oct 12 12:35:18 AM UTC 24 80251712 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2053373778 Oct 12 12:35:10 AM UTC 24 Oct 12 12:35:18 AM UTC 24 261326787 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1281459270 Oct 12 12:35:14 AM UTC 24 Oct 12 12:35:20 AM UTC 24 429953043 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1748915014 Oct 12 12:35:18 AM UTC 24 Oct 12 12:35:21 AM UTC 24 119208385 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2820167514 Oct 12 12:35:19 AM UTC 24 Oct 12 12:35:21 AM UTC 24 44489819 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3195240940 Oct 12 12:35:19 AM UTC 24 Oct 12 12:35:22 AM UTC 24 73983814 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2033943057 Oct 12 12:35:19 AM UTC 24 Oct 12 12:35:24 AM UTC 24 238643251 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2979700003 Oct 12 12:35:19 AM UTC 24 Oct 12 12:35:24 AM UTC 24 246131520 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.2858948807 Oct 12 12:35:21 AM UTC 24 Oct 12 12:35:24 AM UTC 24 60578568 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.1702021950 Oct 12 12:35:22 AM UTC 24 Oct 12 12:35:24 AM UTC 24 25691012 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2978845394 Oct 12 12:35:22 AM UTC 24 Oct 12 12:35:24 AM UTC 24 28875153 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1852076095 Oct 12 12:35:21 AM UTC 24 Oct 12 12:35:25 AM UTC 24 153239980 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.1349375690 Oct 12 12:35:32 AM UTC 24 Oct 12 12:35:35 AM UTC 24 17289433 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3012341469 Oct 12 12:35:18 AM UTC 24 Oct 12 12:35:36 AM UTC 24 3229073318 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3447011007 Oct 12 12:35:35 AM UTC 24 Oct 12 12:35:37 AM UTC 24 103305820 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.3890235589 Oct 12 12:35:36 AM UTC 24 Oct 12 12:35:38 AM UTC 24 12178311 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.55493854 Oct 12 12:35:32 AM UTC 24 Oct 12 12:35:38 AM UTC 24 352598262 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.715133169 Oct 12 12:35:35 AM UTC 24 Oct 12 12:35:38 AM UTC 24 83981461 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3636768115 Oct 12 12:35:34 AM UTC 24 Oct 12 12:35:38 AM UTC 24 122858604 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2002332742 Oct 12 12:35:35 AM UTC 24 Oct 12 12:35:39 AM UTC 24 67629175 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3959207384 Oct 12 12:35:34 AM UTC 24 Oct 12 12:35:39 AM UTC 24 140543499 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.3844776367 Oct 12 12:35:37 AM UTC 24 Oct 12 12:35:39 AM UTC 24 26359577 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.4094100288 Oct 12 12:35:35 AM UTC 24 Oct 12 12:35:40 AM UTC 24 115585878 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2706058522 Oct 12 12:35:38 AM UTC 24 Oct 12 12:35:41 AM UTC 24 63849324 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.4060187677 Oct 12 12:35:35 AM UTC 24 Oct 12 12:35:42 AM UTC 24 420107868 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1408465403 Oct 12 12:35:39 AM UTC 24 Oct 12 12:35:42 AM UTC 24 75175147 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.4244179594 Oct 12 12:35:39 AM UTC 24 Oct 12 12:35:42 AM UTC 24 95652291 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.176426081 Oct 12 12:35:40 AM UTC 24 Oct 12 12:35:43 AM UTC 24 33625652 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.1727337846 Oct 12 12:35:41 AM UTC 24 Oct 12 12:35:43 AM UTC 24 26405590 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2233525324 Oct 12 12:35:39 AM UTC 24 Oct 12 12:35:44 AM UTC 24 140777307 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.201372305 Oct 12 12:35:39 AM UTC 24 Oct 12 12:35:44 AM UTC 24 100583734 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2702138216 Oct 12 12:35:42 AM UTC 24 Oct 12 12:35:44 AM UTC 24 60422741 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.2813618638 Oct 12 12:35:39 AM UTC 24 Oct 12 12:35:45 AM UTC 24 251835409 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1469804011 Oct 12 12:35:43 AM UTC 24 Oct 12 12:35:46 AM UTC 24 109814207 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3681101357 Oct 12 12:35:43 AM UTC 24 Oct 12 12:35:46 AM UTC 24 238382985 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.993804224 Oct 12 12:35:43 AM UTC 24 Oct 12 12:35:46 AM UTC 24 59646638 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.492844493 Oct 12 12:35:45 AM UTC 24 Oct 12 12:35:47 AM UTC 24 21129385 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.1791642652 Oct 12 12:35:45 AM UTC 24 Oct 12 12:35:47 AM UTC 24 38420304 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2829445321 Oct 12 12:35:45 AM UTC 24 Oct 12 12:35:48 AM UTC 24 27697787 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1437334395 Oct 12 12:35:45 AM UTC 24 Oct 12 12:35:49 AM UTC 24 216006209 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.1749558236 Oct 12 12:35:48 AM UTC 24 Oct 12 12:35:51 AM UTC 24 21497013 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.3012623405 Oct 12 12:35:47 AM UTC 24 Oct 12 12:35:49 AM UTC 24 26065337 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1598956884 Oct 12 12:35:46 AM UTC 24 Oct 12 12:35:49 AM UTC 24 76799803 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1564983416 Oct 12 12:35:45 AM UTC 24 Oct 12 12:35:49 AM UTC 24 358803155 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.2010041870 Oct 12 12:35:45 AM UTC 24 Oct 12 12:35:49 AM UTC 24 64612839 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3446609741 Oct 12 12:35:45 AM UTC 24 Oct 12 12:35:50 AM UTC 24 486481247 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3830021985 Oct 12 12:35:47 AM UTC 24 Oct 12 12:35:51 AM UTC 24 88575277 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.3296089875 Oct 12 12:35:47 AM UTC 24 Oct 12 12:35:51 AM UTC 24 186520179 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2329587969 Oct 12 12:35:49 AM UTC 24 Oct 12 12:35:51 AM UTC 24 93544570 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1098460326 Oct 12 12:35:49 AM UTC 24 Oct 12 12:35:51 AM UTC 24 52284435 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.2480997843 Oct 12 12:35:51 AM UTC 24 Oct 12 12:35:53 AM UTC 24 13371046 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.939172494 Oct 12 12:35:50 AM UTC 24 Oct 12 12:35:53 AM UTC 24 260052671 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.2225686039 Oct 12 12:35:51 AM UTC 24 Oct 12 12:35:53 AM UTC 24 56098346 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3433510933 Oct 12 12:35:52 AM UTC 24 Oct 12 12:35:55 AM UTC 24 148372357 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2658708970 Oct 12 12:35:51 AM UTC 24 Oct 12 12:35:56 AM UTC 24 139326131 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1898499701 Oct 12 12:35:52 AM UTC 24 Oct 12 12:35:56 AM UTC 24 180783317 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3147136216 Oct 12 12:35:52 AM UTC 24 Oct 12 12:35:56 AM UTC 24 187023657 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.4219559314 Oct 12 12:35:51 AM UTC 24 Oct 12 12:35:56 AM UTC 24 250500728 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.639074508 Oct 12 12:35:55 AM UTC 24 Oct 12 12:35:57 AM UTC 24 59690800 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.3245954266 Oct 12 12:35:52 AM UTC 24 Oct 12 12:35:57 AM UTC 24 116052027 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.809419551 Oct 12 12:35:51 AM UTC 24 Oct 12 12:35:57 AM UTC 24 451890036 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1236747253 Oct 12 12:35:55 AM UTC 24 Oct 12 12:35:57 AM UTC 24 20870329 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2162970720 Oct 12 12:35:53 AM UTC 24 Oct 12 12:35:57 AM UTC 24 153161689 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1511078001 Oct 12 12:35:56 AM UTC 24 Oct 12 12:35:58 AM UTC 24 98453917 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1732519033 Oct 12 12:35:52 AM UTC 24 Oct 12 12:35:59 AM UTC 24 419563911 ps
T920 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3295588849 Oct 12 12:35:57 AM UTC 24 Oct 12 12:35:59 AM UTC 24 32285906 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.3784495924 Oct 12 12:36:16 AM UTC 24 Oct 12 12:36:20 AM UTC 24 26911151 ps
T922 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.379630196 Oct 12 12:35:57 AM UTC 24 Oct 12 12:36:00 AM UTC 24 59248238 ps
T923 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.1683462969 Oct 12 12:35:58 AM UTC 24 Oct 12 12:36:00 AM UTC 24 21809553 ps
T924 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.251631050 Oct 12 12:35:58 AM UTC 24 Oct 12 12:36:00 AM UTC 24 22652410 ps
T925 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2281848763 Oct 12 12:35:58 AM UTC 24 Oct 12 12:36:01 AM UTC 24 22758437 ps
T926 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.452994405 Oct 12 12:35:57 AM UTC 24 Oct 12 12:36:01 AM UTC 24 121089541 ps
T927 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.13333140 Oct 12 12:35:58 AM UTC 24 Oct 12 12:36:01 AM UTC 24 92052419 ps
T928 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.2252527078 Oct 12 12:35:57 AM UTC 24 Oct 12 12:36:01 AM UTC 24 129781951 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.4029312560 Oct 12 12:35:59 AM UTC 24 Oct 12 12:36:02 AM UTC 24 86902638 ps
T929 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.3696681322 Oct 12 12:36:02 AM UTC 24 Oct 12 12:36:04 AM UTC 24 20018597 ps
T930 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.1344356403 Oct 12 12:36:02 AM UTC 24 Oct 12 12:36:04 AM UTC 24 43419877 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1466902546 Oct 12 12:35:59 AM UTC 24 Oct 12 12:36:04 AM UTC 24 103108590 ps
T931 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.987732849 Oct 12 12:36:02 AM UTC 24 Oct 12 12:36:04 AM UTC 24 25562414 ps
T932 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.289659468 Oct 12 12:36:02 AM UTC 24 Oct 12 12:36:05 AM UTC 24 154148842 ps
T933 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.1616082934 Oct 12 12:36:00 AM UTC 24 Oct 12 12:36:06 AM UTC 24 273493024 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.877071480 Oct 12 12:36:01 AM UTC 24 Oct 12 12:36:06 AM UTC 24 126053764 ps
T934 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.1259181436 Oct 12 12:36:04 AM UTC 24 Oct 12 12:36:06 AM UTC 24 13533243 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3558570443 Oct 12 12:36:03 AM UTC 24 Oct 12 12:36:06 AM UTC 24 65967499 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3411424509 Oct 12 12:35:58 AM UTC 24 Oct 12 12:36:06 AM UTC 24 978582288 ps
T935 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1427455308 Oct 12 12:36:03 AM UTC 24 Oct 12 12:36:07 AM UTC 24 95795569 ps
T936 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.1372052885 Oct 12 12:36:03 AM UTC 24 Oct 12 12:36:08 AM UTC 24 81669401 ps
T937 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.2174923051 Oct 12 12:36:05 AM UTC 24 Oct 12 12:36:08 AM UTC 24 23123997 ps
T938 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.343518671 Oct 12 12:36:05 AM UTC 24 Oct 12 12:36:08 AM UTC 24 24964679 ps
T939 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.937272258 Oct 12 12:36:05 AM UTC 24 Oct 12 12:36:09 AM UTC 24 54365442 ps
T940 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.3390506987 Oct 12 12:36:08 AM UTC 24 Oct 12 12:36:10 AM UTC 24 33497821 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3715494840 Oct 12 12:36:06 AM UTC 24 Oct 12 12:36:10 AM UTC 24 110516914 ps
T941 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.3866693861 Oct 12 12:36:08 AM UTC 24 Oct 12 12:36:10 AM UTC 24 24475786 ps
T942 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.946231555 Oct 12 12:36:15 AM UTC 24 Oct 12 12:36:19 AM UTC 24 151207764 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1280954066 Oct 12 12:36:04 AM UTC 24 Oct 12 12:36:11 AM UTC 24 725256283 ps
T943 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3047858361 Oct 12 12:36:07 AM UTC 24 Oct 12 12:36:11 AM UTC 24 167025696 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2216177151 Oct 12 12:36:07 AM UTC 24 Oct 12 12:36:11 AM UTC 24 104689859 ps
T944 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.3348483854 Oct 12 12:36:07 AM UTC 24 Oct 12 12:36:11 AM UTC 24 190621123 ps
T945 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1334438277 Oct 12 12:36:08 AM UTC 24 Oct 12 12:36:12 AM UTC 24 56848647 ps
T946 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1394270762 Oct 12 12:36:09 AM UTC 24 Oct 12 12:36:12 AM UTC 24 125887695 ps
T947 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.3279522503 Oct 12 12:36:10 AM UTC 24 Oct 12 12:36:13 AM UTC 24 28751993 ps
T948 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1315611478 Oct 12 12:36:09 AM UTC 24 Oct 12 12:36:13 AM UTC 24 153838917 ps
T949 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.2823839205 Oct 12 12:36:11 AM UTC 24 Oct 12 12:36:13 AM UTC 24 17613972 ps
T950 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.3081132260 Oct 12 12:36:11 AM UTC 24 Oct 12 12:36:14 AM UTC 24 45287950 ps
T951 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.836678051 Oct 12 12:36:09 AM UTC 24 Oct 12 12:36:14 AM UTC 24 315683377 ps
T952 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1467300282 Oct 12 12:36:12 AM UTC 24 Oct 12 12:36:15 AM UTC 24 85392836 ps
T953 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2338930218 Oct 12 12:36:13 AM UTC 24 Oct 12 12:36:16 AM UTC 24 155748090 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3681869630 Oct 12 12:36:11 AM UTC 24 Oct 12 12:36:16 AM UTC 24 140564074 ps
T954 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.544389387 Oct 12 12:36:14 AM UTC 24 Oct 12 12:36:16 AM UTC 24 33049213 ps
T955 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.1073345649 Oct 12 12:36:14 AM UTC 24 Oct 12 12:36:16 AM UTC 24 42306182 ps
T956 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1628967959 Oct 12 12:36:14 AM UTC 24 Oct 12 12:36:16 AM UTC 24 59012965 ps
T957 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.3053600137 Oct 12 12:36:13 AM UTC 24 Oct 12 12:36:18 AM UTC 24 75840493 ps
T958 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4065385766 Oct 12 12:36:14 AM UTC 24 Oct 12 12:36:18 AM UTC 24 69990753 ps
T959 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.3074709664 Oct 12 12:36:17 AM UTC 24 Oct 12 12:36:19 AM UTC 24 14865998 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1934414645 Oct 12 12:36:13 AM UTC 24 Oct 12 12:36:19 AM UTC 24 709501794 ps
T960 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.113248952 Oct 12 12:36:15 AM UTC 24 Oct 12 12:36:19 AM UTC 24 113471126 ps
T961 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.3840314926 Oct 12 12:36:18 AM UTC 24 Oct 12 12:36:20 AM UTC 24 104024382 ps
T962 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1657165578 Oct 12 12:36:18 AM UTC 24 Oct 12 12:36:20 AM UTC 24 64774513 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3316343801 Oct 12 12:36:13 AM UTC 24 Oct 12 12:36:21 AM UTC 24 531526856 ps
T963 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.2807531795 Oct 12 12:36:19 AM UTC 24 Oct 12 12:36:21 AM UTC 24 42679998 ps
T964 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.4108811143 Oct 12 12:36:13 AM UTC 24 Oct 12 12:36:22 AM UTC 24 674119482 ps
T965 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.3341836406 Oct 12 12:36:20 AM UTC 24 Oct 12 12:36:22 AM UTC 24 37633609 ps
T966 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1026530606 Oct 12 12:36:19 AM UTC 24 Oct 12 12:36:23 AM UTC 24 285182387 ps
T967 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1243605078 Oct 12 12:36:17 AM UTC 24 Oct 12 12:36:23 AM UTC 24 367998963 ps
T968 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.1059904011 Oct 12 12:36:21 AM UTC 24 Oct 12 12:36:23 AM UTC 24 20106788 ps
T969 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2353009962 Oct 12 12:36:20 AM UTC 24 Oct 12 12:36:24 AM UTC 24 70137079 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.367542801 Oct 12 12:36:21 AM UTC 24 Oct 12 12:36:24 AM UTC 24 48011697 ps
T970 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3814733290 Oct 12 12:36:21 AM UTC 24 Oct 12 12:36:24 AM UTC 24 24626173 ps
T971 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2649546352 Oct 12 12:36:21 AM UTC 24 Oct 12 12:36:25 AM UTC 24 40654914 ps
T972 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2883836274 Oct 12 12:36:20 AM UTC 24 Oct 12 12:36:25 AM UTC 24 599070220 ps
T973 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3176840503 Oct 12 12:36:20 AM UTC 24 Oct 12 12:36:25 AM UTC 24 227844331 ps
T974 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.539017547 Oct 12 12:36:23 AM UTC 24 Oct 12 12:36:26 AM UTC 24 13753989 ps
T975 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.1510873707 Oct 12 12:36:24 AM UTC 24 Oct 12 12:36:26 AM UTC 24 48505147 ps
T976 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.2866785833 Oct 12 12:36:23 AM UTC 24 Oct 12 12:36:27 AM UTC 24 159762884 ps
T977 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.294410976 Oct 12 12:36:23 AM UTC 24 Oct 12 12:36:27 AM UTC 24 76936893 ps
T978 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.1234802514 Oct 12 12:36:25 AM UTC 24 Oct 12 12:36:27 AM UTC 24 12390412 ps
T979 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.1845301076 Oct 12 12:36:25 AM UTC 24 Oct 12 12:36:27 AM UTC 24 37843386 ps
T980 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.2410240882 Oct 12 12:36:25 AM UTC 24 Oct 12 12:36:27 AM UTC 24 28038006 ps
T981 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1414045497 Oct 12 12:36:25 AM UTC 24 Oct 12 12:36:27 AM UTC 24 52323146 ps
T982 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3720271110 Oct 12 12:36:25 AM UTC 24 Oct 12 12:36:27 AM UTC 24 82884513 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.117736201 Oct 12 12:36:23 AM UTC 24 Oct 12 12:36:28 AM UTC 24 381523210 ps
T983 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.2729375057 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:33 AM UTC 24 14647603 ps
T984 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.4281416365 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:33 AM UTC 24 12630842 ps
T985 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.2457268534 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:33 AM UTC 24 23739824 ps
T986 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.449019152 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:33 AM UTC 24 21218785 ps
T987 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.1069497043 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:33 AM UTC 24 13873909 ps
T988 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.2975119160 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:33 AM UTC 24 17826210 ps
T989 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.2181681033 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:33 AM UTC 24 10916503 ps
T990 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.4030422163 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:34 AM UTC 24 15459179 ps
T991 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.1711138097 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:34 AM UTC 24 12052843 ps
T992 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.1700098891 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:34 AM UTC 24 12902091 ps
T993 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.2663562334 Oct 12 12:36:31 AM UTC 24 Oct 12 12:36:34 AM UTC 24 30108649 ps
T994 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.3476829810 Oct 12 12:36:32 AM UTC 24 Oct 12 12:36:34 AM UTC 24 15956417 ps
T995 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.893490575 Oct 12 12:36:32 AM UTC 24 Oct 12 12:36:34 AM UTC 24 11412756 ps
T996 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.3772201995 Oct 12 12:36:32 AM UTC 24 Oct 12 12:36:34 AM UTC 24 37380453 ps
T997 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.989537044 Oct 12 12:36:32 AM UTC 24 Oct 12 12:36:34 AM UTC 24 26003675 ps
T998 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.3013480153 Oct 12 12:36:32 AM UTC 24 Oct 12 12:36:34 AM UTC 24 64223674 ps
T999 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.3146207364 Oct 12 12:36:34 AM UTC 24 Oct 12 12:36:36 AM UTC 24 23586422 ps
T1000 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.1069943892 Oct 12 12:36:34 AM UTC 24 Oct 12 12:36:36 AM UTC 24 12125371 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%