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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1009
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T1001 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.2176868762 Oct 12 12:36:34 AM UTC 24 Oct 12 12:36:36 AM UTC 24 27065028 ps
T1002 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.2014578032 Oct 12 12:36:34 AM UTC 24 Oct 12 12:36:36 AM UTC 24 12496382 ps
T1003 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.2045072529 Oct 12 12:36:34 AM UTC 24 Oct 12 12:36:36 AM UTC 24 14296432 ps
T1004 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.2358992915 Oct 12 12:36:34 AM UTC 24 Oct 12 12:36:37 AM UTC 24 39918855 ps
T1005 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.4156618118 Oct 12 12:36:34 AM UTC 24 Oct 12 12:36:37 AM UTC 24 97268243 ps
T1006 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.1127464731 Oct 12 12:36:35 AM UTC 24 Oct 12 12:36:37 AM UTC 24 20050728 ps
T1007 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.1928232689 Oct 12 12:36:35 AM UTC 24 Oct 12 12:36:37 AM UTC 24 14947315 ps
T1008 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.3044343221 Oct 12 12:36:36 AM UTC 24 Oct 12 12:36:38 AM UTC 24 12625241 ps
T1009 /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1415129902 Oct 12 12:36:36 AM UTC 24 Oct 12 12:36:38 AM UTC 24 12211757 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.2315726588
Short name T26
Test name
Test status
Simulation time 77417502 ps
CPU time 1.01 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315726588 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2315726588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.896698388
Short name T17
Test name
Test status
Simulation time 1351408937 ps
CPU time 5.28 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896698388 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.896698388
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.241546332
Short name T23
Test name
Test status
Simulation time 1384964359 ps
CPU time 5.92 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241546332 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.241546332
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.783303946
Short name T15
Test name
Test status
Simulation time 4055113212 ps
CPU time 24.01 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:53:13 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783303946 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.783303946
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.3466138839
Short name T77
Test name
Test status
Simulation time 75301928 ps
CPU time 0.99 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466138839 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.3466138839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.4083521474
Short name T59
Test name
Test status
Simulation time 2240148461 ps
CPU time 29.47 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:39 AM UTC 24
Peak memory 225544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083521474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.4083521474
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3353369279
Short name T114
Test name
Test status
Simulation time 100523308 ps
CPU time 3.18 seconds
Started Oct 12 12:35:11 AM UTC 24
Finished Oct 12 12:35:15 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353369
279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.3353369279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.2593955747
Short name T98
Test name
Test status
Simulation time 159981643 ps
CPU time 1.97 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:50 AM UTC 24
Peak memory 241460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593955747 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.2593955747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.1373583072
Short name T4
Test name
Test status
Simulation time 13706208 ps
CPU time 0.63 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 210744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373583072 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1373583072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.2475524662
Short name T49
Test name
Test status
Simulation time 30183804 ps
CPU time 0.92 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475524662 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.2475524662
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.4291991398
Short name T25
Test name
Test status
Simulation time 21120544 ps
CPU time 0.82 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291991398
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.4291991398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1092262003
Short name T116
Test name
Test status
Simulation time 128286274 ps
CPU time 3.54 seconds
Started Oct 12 12:34:37 AM UTC 24
Finished Oct 12 12:34:42 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092262003 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.1092262003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.2617380327
Short name T11
Test name
Test status
Simulation time 1057402807 ps
CPU time 5.25 seconds
Started Oct 12 12:52:57 AM UTC 24
Finished Oct 12 12:53:03 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617380327 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2617380327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4208595992
Short name T81
Test name
Test status
Simulation time 99703956 ps
CPU time 2.95 seconds
Started Oct 12 12:34:35 AM UTC 24
Finished Oct 12 12:34:39 AM UTC 24
Peak memory 219700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4208595992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_
errors_with_csr_rw.4208595992
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.1671871220
Short name T213
Test name
Test status
Simulation time 21176581 ps
CPU time 0.76 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671871220 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1671871220
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1569106710
Short name T50
Test name
Test status
Simulation time 53949978 ps
CPU time 0.87 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569106710
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.1569106710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.1809175731
Short name T73
Test name
Test status
Simulation time 30449969 ps
CPU time 0.73 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809175731 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.1809175731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1234567981
Short name T30
Test name
Test status
Simulation time 28713080 ps
CPU time 0.85 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234567981 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.1234567981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2658708970
Short name T203
Test name
Test status
Simulation time 139326131 ps
CPU time 3.73 seconds
Started Oct 12 12:35:51 AM UTC 24
Finished Oct 12 12:35:56 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658708970 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.2658708970
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3715494840
Short name T152
Test name
Test status
Simulation time 110516914 ps
CPU time 3.5 seconds
Started Oct 12 12:36:06 AM UTC 24
Finished Oct 12 12:36:10 AM UTC 24
Peak memory 219756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715494
840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.3715494840
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.2128955975
Short name T181
Test name
Test status
Simulation time 12597214378 ps
CPU time 66.37 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:54:10 AM UTC 24
Peak memory 221824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128955975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.2128955975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.1105388276
Short name T7
Test name
Test status
Simulation time 370547442 ps
CPU time 2.72 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:15 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105388276 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1105388276
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.4080075200
Short name T65
Test name
Test status
Simulation time 858628502 ps
CPU time 4.38 seconds
Started Oct 12 12:53:24 AM UTC 24
Finished Oct 12 12:53:30 AM UTC 24
Peak memory 211724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080075200 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.4080075200
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.2854395333
Short name T1
Test name
Test status
Simulation time 327071764 ps
CPU time 2.79 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:50 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854395333 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2854395333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.3372346351
Short name T268
Test name
Test status
Simulation time 155374376 ps
CPU time 1.41 seconds
Started Oct 12 12:53:09 AM UTC 24
Finished Oct 12 12:53:12 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372346351 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.3372346351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.1271110762
Short name T305
Test name
Test status
Simulation time 954223242 ps
CPU time 4.86 seconds
Started Oct 12 12:53:16 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271110762 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1271110762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3433510933
Short name T142
Test name
Test status
Simulation time 148372357 ps
CPU time 1.97 seconds
Started Oct 12 12:35:52 AM UTC 24
Finished Oct 12 12:35:55 AM UTC 24
Peak memory 218632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3433510933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg
_errors_with_csr_rw.3433510933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.4029312560
Short name T154
Test name
Test status
Simulation time 86902638 ps
CPU time 2 seconds
Started Oct 12 12:35:59 AM UTC 24
Finished Oct 12 12:36:02 AM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029312
560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.4029312560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2216177151
Short name T126
Test name
Test status
Simulation time 104689859 ps
CPU time 3.55 seconds
Started Oct 12 12:36:07 AM UTC 24
Finished Oct 12 12:36:11 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216177151 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.2216177151
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3681869630
Short name T121
Test name
Test status
Simulation time 140564074 ps
CPU time 3.51 seconds
Started Oct 12 12:36:11 AM UTC 24
Finished Oct 12 12:36:16 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681869630 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.3681869630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.532357747
Short name T105
Test name
Test status
Simulation time 6370886533 ps
CPU time 44.58 seconds
Started Oct 12 12:53:21 AM UTC 24
Finished Oct 12 12:54:10 AM UTC 24
Peak memory 211888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532357747 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.532357747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1281459270
Short name T120
Test name
Test status
Simulation time 429953043 ps
CPU time 4.95 seconds
Started Oct 12 12:35:14 AM UTC 24
Finished Oct 12 12:35:20 AM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281459270 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.1281459270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.4240021778
Short name T857
Test name
Test status
Simulation time 624253248 ps
CPU time 5.46 seconds
Started Oct 12 12:34:43 AM UTC 24
Finished Oct 12 12:34:50 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240021778 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.4240021778
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3737169452
Short name T862
Test name
Test status
Simulation time 418927218 ps
CPU time 13.73 seconds
Started Oct 12 12:34:43 AM UTC 24
Finished Oct 12 12:34:58 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737169452 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.3737169452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.554514127
Short name T122
Test name
Test status
Simulation time 16145206 ps
CPU time 1.17 seconds
Started Oct 12 12:34:40 AM UTC 24
Finished Oct 12 12:34:42 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554514127 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.554514127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3428888309
Short name T856
Test name
Test status
Simulation time 29942120 ps
CPU time 1.4 seconds
Started Oct 12 12:34:45 AM UTC 24
Finished Oct 12 12:34:47 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3428888309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_csr_mem_rw_with_rand_reset.3428888309
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.493069070
Short name T82
Test name
Test status
Simulation time 16203370 ps
CPU time 1.21 seconds
Started Oct 12 12:34:42 AM UTC 24
Finished Oct 12 12:34:44 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493069070 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.493069070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.1454908538
Short name T855
Test name
Test status
Simulation time 19566547 ps
CPU time 1.08 seconds
Started Oct 12 12:34:40 AM UTC 24
Finished Oct 12 12:34:42 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454908538 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.1454908538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4167024558
Short name T83
Test name
Test status
Simulation time 55260233 ps
CPU time 1.7 seconds
Started Oct 12 12:34:45 AM UTC 24
Finished Oct 12 12:34:48 AM UTC 24
Peak memory 209680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167
024558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.4167024558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.777754499
Short name T111
Test name
Test status
Simulation time 93636781 ps
CPU time 1.96 seconds
Started Oct 12 12:34:33 AM UTC 24
Finished Oct 12 12:34:36 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7777544
99 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.777754499
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.1618848056
Short name T854
Test name
Test status
Simulation time 77331366 ps
CPU time 2.04 seconds
Started Oct 12 12:34:36 AM UTC 24
Finished Oct 12 12:34:39 AM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618848056 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.1618848056
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1299359743
Short name T85
Test name
Test status
Simulation time 75981852 ps
CPU time 2.07 seconds
Started Oct 12 12:34:56 AM UTC 24
Finished Oct 12 12:34:59 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299359743 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.1299359743
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1625792742
Short name T865
Test name
Test status
Simulation time 753853967 ps
CPU time 9.41 seconds
Started Oct 12 12:34:56 AM UTC 24
Finished Oct 12 12:35:06 AM UTC 24
Peak memory 210016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625792742 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.1625792742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3678129693
Short name T860
Test name
Test status
Simulation time 35303526 ps
CPU time 1.43 seconds
Started Oct 12 12:34:53 AM UTC 24
Finished Oct 12 12:34:55 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678129693 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.3678129693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1812994654
Short name T863
Test name
Test status
Simulation time 53638199 ps
CPU time 1.71 seconds
Started Oct 12 12:34:57 AM UTC 24
Finished Oct 12 12:35:00 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1812994654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_csr_mem_rw_with_rand_reset.1812994654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.1114038793
Short name T861
Test name
Test status
Simulation time 29533013 ps
CPU time 1.23 seconds
Started Oct 12 12:34:54 AM UTC 24
Finished Oct 12 12:34:56 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114038793 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.1114038793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.2850040235
Short name T859
Test name
Test status
Simulation time 58337474 ps
CPU time 1.18 seconds
Started Oct 12 12:34:53 AM UTC 24
Finished Oct 12 12:34:55 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850040235 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.2850040235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3818452400
Short name T86
Test name
Test status
Simulation time 100372776 ps
CPU time 1.79 seconds
Started Oct 12 12:34:57 AM UTC 24
Finished Oct 12 12:35:00 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818
452400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.3818452400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3758436468
Short name T112
Test name
Test status
Simulation time 91367627 ps
CPU time 2.52 seconds
Started Oct 12 12:34:48 AM UTC 24
Finished Oct 12 12:34:52 AM UTC 24
Peak memory 219756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758436
468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.3758436468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3275019521
Short name T84
Test name
Test status
Simulation time 231214961 ps
CPU time 3.36 seconds
Started Oct 12 12:34:48 AM UTC 24
Finished Oct 12 12:34:53 AM UTC 24
Peak memory 219760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3275019521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_
errors_with_csr_rw.3275019521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.869817895
Short name T858
Test name
Test status
Simulation time 47834645 ps
CPU time 2.54 seconds
Started Oct 12 12:34:48 AM UTC 24
Finished Oct 12 12:34:52 AM UTC 24
Peak memory 210080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869817895 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.869817895
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2123965598
Short name T117
Test name
Test status
Simulation time 217965386 ps
CPU time 5.02 seconds
Started Oct 12 12:34:50 AM UTC 24
Finished Oct 12 12:34:57 AM UTC 24
Peak memory 210040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123965598 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.2123965598
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3295588849
Short name T920
Test name
Test status
Simulation time 32285906 ps
CPU time 1.41 seconds
Started Oct 12 12:35:57 AM UTC 24
Finished Oct 12 12:35:59 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3295588849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_csr_mem_rw_with_rand_reset.3295588849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1236747253
Short name T918
Test name
Test status
Simulation time 20870329 ps
CPU time 1.32 seconds
Started Oct 12 12:35:55 AM UTC 24
Finished Oct 12 12:35:57 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236747253 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.1236747253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.639074508
Short name T915
Test name
Test status
Simulation time 59690800 ps
CPU time 1.11 seconds
Started Oct 12 12:35:55 AM UTC 24
Finished Oct 12 12:35:57 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639074508 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.639074508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1511078001
Short name T919
Test name
Test status
Simulation time 98453917 ps
CPU time 1.39 seconds
Started Oct 12 12:35:56 AM UTC 24
Finished Oct 12 12:35:58 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511
078001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.1511078001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1732519033
Short name T151
Test name
Test status
Simulation time 419563911 ps
CPU time 5.39 seconds
Started Oct 12 12:35:52 AM UTC 24
Finished Oct 12 12:35:59 AM UTC 24
Peak memory 219764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732519
033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.1732519033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.3245954266
Short name T916
Test name
Test status
Simulation time 116052027 ps
CPU time 3.33 seconds
Started Oct 12 12:35:52 AM UTC 24
Finished Oct 12 12:35:57 AM UTC 24
Peak memory 210152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245954266 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.3245954266
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2162970720
Short name T130
Test name
Test status
Simulation time 153161689 ps
CPU time 2.46 seconds
Started Oct 12 12:35:53 AM UTC 24
Finished Oct 12 12:35:57 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162970720 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.2162970720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.13333140
Short name T927
Test name
Test status
Simulation time 92052419 ps
CPU time 2.03 seconds
Started Oct 12 12:35:58 AM UTC 24
Finished Oct 12 12:36:01 AM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=13333140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.clkmgr_csr_mem_rw_with_rand_reset.13333140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.1683462969
Short name T923
Test name
Test status
Simulation time 21809553 ps
CPU time 1.1 seconds
Started Oct 12 12:35:58 AM UTC 24
Finished Oct 12 12:36:00 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683462969 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.1683462969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.251631050
Short name T924
Test name
Test status
Simulation time 22652410 ps
CPU time 1.16 seconds
Started Oct 12 12:35:58 AM UTC 24
Finished Oct 12 12:36:00 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251631050 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.251631050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2281848763
Short name T925
Test name
Test status
Simulation time 22758437 ps
CPU time 1.2 seconds
Started Oct 12 12:35:58 AM UTC 24
Finished Oct 12 12:36:01 AM UTC 24
Peak memory 209540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281
848763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.2281848763
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.452994405
Short name T926
Test name
Test status
Simulation time 121089541 ps
CPU time 3.13 seconds
Started Oct 12 12:35:57 AM UTC 24
Finished Oct 12 12:36:01 AM UTC 24
Peak memory 219620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4529944
05 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.452994405
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.379630196
Short name T922
Test name
Test status
Simulation time 59248238 ps
CPU time 2.1 seconds
Started Oct 12 12:35:57 AM UTC 24
Finished Oct 12 12:36:00 AM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=379630196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_
errors_with_csr_rw.379630196
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.2252527078
Short name T928
Test name
Test status
Simulation time 129781951 ps
CPU time 3.41 seconds
Started Oct 12 12:35:57 AM UTC 24
Finished Oct 12 12:36:01 AM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252527078 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.2252527078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3411424509
Short name T123
Test name
Test status
Simulation time 978582288 ps
CPU time 7.23 seconds
Started Oct 12 12:35:58 AM UTC 24
Finished Oct 12 12:36:06 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411424509 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.3411424509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.289659468
Short name T932
Test name
Test status
Simulation time 154148842 ps
CPU time 1.82 seconds
Started Oct 12 12:36:02 AM UTC 24
Finished Oct 12 12:36:05 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=289659468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.clkmgr_csr_mem_rw_with_rand_reset.289659468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.1344356403
Short name T930
Test name
Test status
Simulation time 43419877 ps
CPU time 1.27 seconds
Started Oct 12 12:36:02 AM UTC 24
Finished Oct 12 12:36:04 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344356403 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.1344356403
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.3696681322
Short name T929
Test name
Test status
Simulation time 20018597 ps
CPU time 1.11 seconds
Started Oct 12 12:36:02 AM UTC 24
Finished Oct 12 12:36:04 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696681322 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.3696681322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.987732849
Short name T931
Test name
Test status
Simulation time 25562414 ps
CPU time 1.63 seconds
Started Oct 12 12:36:02 AM UTC 24
Finished Oct 12 12:36:04 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9877
32849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.987732849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1466902546
Short name T156
Test name
Test status
Simulation time 103108590 ps
CPU time 3.88 seconds
Started Oct 12 12:35:59 AM UTC 24
Finished Oct 12 12:36:04 AM UTC 24
Peak memory 219624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1466902546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg
_errors_with_csr_rw.1466902546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.1616082934
Short name T933
Test name
Test status
Simulation time 273493024 ps
CPU time 4.23 seconds
Started Oct 12 12:36:00 AM UTC 24
Finished Oct 12 12:36:06 AM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616082934 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.1616082934
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.877071480
Short name T125
Test name
Test status
Simulation time 126053764 ps
CPU time 4.43 seconds
Started Oct 12 12:36:01 AM UTC 24
Finished Oct 12 12:36:06 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877071480 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.877071480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.343518671
Short name T938
Test name
Test status
Simulation time 24964679 ps
CPU time 1.88 seconds
Started Oct 12 12:36:05 AM UTC 24
Finished Oct 12 12:36:08 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=343518671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.clkmgr_csr_mem_rw_with_rand_reset.343518671
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.2174923051
Short name T937
Test name
Test status
Simulation time 23123997 ps
CPU time 1.29 seconds
Started Oct 12 12:36:05 AM UTC 24
Finished Oct 12 12:36:08 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174923051 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.2174923051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.1259181436
Short name T934
Test name
Test status
Simulation time 13533243 ps
CPU time 0.94 seconds
Started Oct 12 12:36:04 AM UTC 24
Finished Oct 12 12:36:06 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259181436 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.1259181436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.937272258
Short name T939
Test name
Test status
Simulation time 54365442 ps
CPU time 2.22 seconds
Started Oct 12 12:36:05 AM UTC 24
Finished Oct 12 12:36:09 AM UTC 24
Peak memory 210068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9372
72258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.937272258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3558570443
Short name T155
Test name
Test status
Simulation time 65967499 ps
CPU time 2.41 seconds
Started Oct 12 12:36:03 AM UTC 24
Finished Oct 12 12:36:06 AM UTC 24
Peak memory 210280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558570
443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.3558570443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1427455308
Short name T935
Test name
Test status
Simulation time 95795569 ps
CPU time 3.19 seconds
Started Oct 12 12:36:03 AM UTC 24
Finished Oct 12 12:36:07 AM UTC 24
Peak memory 219756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1427455308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg
_errors_with_csr_rw.1427455308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.1372052885
Short name T936
Test name
Test status
Simulation time 81669401 ps
CPU time 3.55 seconds
Started Oct 12 12:36:03 AM UTC 24
Finished Oct 12 12:36:08 AM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372052885 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.1372052885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1280954066
Short name T128
Test name
Test status
Simulation time 725256283 ps
CPU time 5.61 seconds
Started Oct 12 12:36:04 AM UTC 24
Finished Oct 12 12:36:11 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280954066 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.1280954066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1394270762
Short name T946
Test name
Test status
Simulation time 125887695 ps
CPU time 2.1 seconds
Started Oct 12 12:36:09 AM UTC 24
Finished Oct 12 12:36:12 AM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1394270762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_csr_mem_rw_with_rand_reset.1394270762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.3866693861
Short name T941
Test name
Test status
Simulation time 24475786 ps
CPU time 1.18 seconds
Started Oct 12 12:36:08 AM UTC 24
Finished Oct 12 12:36:10 AM UTC 24
Peak memory 209128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866693861 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.3866693861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.3390506987
Short name T940
Test name
Test status
Simulation time 33497821 ps
CPU time 1.11 seconds
Started Oct 12 12:36:08 AM UTC 24
Finished Oct 12 12:36:10 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390506987 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.3390506987
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1334438277
Short name T945
Test name
Test status
Simulation time 56848647 ps
CPU time 2.75 seconds
Started Oct 12 12:36:08 AM UTC 24
Finished Oct 12 12:36:12 AM UTC 24
Peak memory 209788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334
438277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.1334438277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3047858361
Short name T943
Test name
Test status
Simulation time 167025696 ps
CPU time 3.44 seconds
Started Oct 12 12:36:07 AM UTC 24
Finished Oct 12 12:36:11 AM UTC 24
Peak memory 221808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3047858361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg
_errors_with_csr_rw.3047858361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.3348483854
Short name T944
Test name
Test status
Simulation time 190621123 ps
CPU time 3.6 seconds
Started Oct 12 12:36:07 AM UTC 24
Finished Oct 12 12:36:11 AM UTC 24
Peak memory 210188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348483854 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.3348483854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2338930218
Short name T953
Test name
Test status
Simulation time 155748090 ps
CPU time 2.27 seconds
Started Oct 12 12:36:13 AM UTC 24
Finished Oct 12 12:36:16 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2338930218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_csr_mem_rw_with_rand_reset.2338930218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.3081132260
Short name T950
Test name
Test status
Simulation time 45287950 ps
CPU time 1.16 seconds
Started Oct 12 12:36:11 AM UTC 24
Finished Oct 12 12:36:14 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081132260 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.3081132260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.2823839205
Short name T949
Test name
Test status
Simulation time 17613972 ps
CPU time 0.98 seconds
Started Oct 12 12:36:11 AM UTC 24
Finished Oct 12 12:36:13 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823839205 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.2823839205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1467300282
Short name T952
Test name
Test status
Simulation time 85392836 ps
CPU time 2.06 seconds
Started Oct 12 12:36:12 AM UTC 24
Finished Oct 12 12:36:15 AM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467
300282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.1467300282
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1315611478
Short name T948
Test name
Test status
Simulation time 153838917 ps
CPU time 3.04 seconds
Started Oct 12 12:36:09 AM UTC 24
Finished Oct 12 12:36:13 AM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315611
478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.1315611478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.836678051
Short name T951
Test name
Test status
Simulation time 315683377 ps
CPU time 4.01 seconds
Started Oct 12 12:36:09 AM UTC 24
Finished Oct 12 12:36:14 AM UTC 24
Peak memory 219688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=836678051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_
errors_with_csr_rw.836678051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.3279522503
Short name T947
Test name
Test status
Simulation time 28751993 ps
CPU time 1.69 seconds
Started Oct 12 12:36:10 AM UTC 24
Finished Oct 12 12:36:13 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279522503 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.3279522503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4065385766
Short name T958
Test name
Test status
Simulation time 69990753 ps
CPU time 3.2 seconds
Started Oct 12 12:36:14 AM UTC 24
Finished Oct 12 12:36:18 AM UTC 24
Peak memory 210148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4065385766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_csr_mem_rw_with_rand_reset.4065385766
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.1073345649
Short name T955
Test name
Test status
Simulation time 42306182 ps
CPU time 1.34 seconds
Started Oct 12 12:36:14 AM UTC 24
Finished Oct 12 12:36:16 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073345649 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.1073345649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.544389387
Short name T954
Test name
Test status
Simulation time 33049213 ps
CPU time 1.06 seconds
Started Oct 12 12:36:14 AM UTC 24
Finished Oct 12 12:36:16 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544389387 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.544389387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1628967959
Short name T956
Test name
Test status
Simulation time 59012965 ps
CPU time 1.37 seconds
Started Oct 12 12:36:14 AM UTC 24
Finished Oct 12 12:36:16 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628
967959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.1628967959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1934414645
Short name T150
Test name
Test status
Simulation time 709501794 ps
CPU time 5 seconds
Started Oct 12 12:36:13 AM UTC 24
Finished Oct 12 12:36:19 AM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934414
645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.1934414645
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.4108811143
Short name T964
Test name
Test status
Simulation time 674119482 ps
CPU time 7.93 seconds
Started Oct 12 12:36:13 AM UTC 24
Finished Oct 12 12:36:22 AM UTC 24
Peak memory 219756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4108811143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg
_errors_with_csr_rw.4108811143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.3053600137
Short name T957
Test name
Test status
Simulation time 75840493 ps
CPU time 3.53 seconds
Started Oct 12 12:36:13 AM UTC 24
Finished Oct 12 12:36:18 AM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053600137 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.3053600137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3316343801
Short name T124
Test name
Test status
Simulation time 531526856 ps
CPU time 6.66 seconds
Started Oct 12 12:36:13 AM UTC 24
Finished Oct 12 12:36:21 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316343801 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.3316343801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.2807531795
Short name T963
Test name
Test status
Simulation time 42679998 ps
CPU time 1.58 seconds
Started Oct 12 12:36:19 AM UTC 24
Finished Oct 12 12:36:21 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2807531795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_csr_mem_rw_with_rand_reset.2807531795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.3840314926
Short name T961
Test name
Test status
Simulation time 104024382 ps
CPU time 1.45 seconds
Started Oct 12 12:36:18 AM UTC 24
Finished Oct 12 12:36:20 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840314926 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.3840314926
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.3074709664
Short name T959
Test name
Test status
Simulation time 14865998 ps
CPU time 1.1 seconds
Started Oct 12 12:36:17 AM UTC 24
Finished Oct 12 12:36:19 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074709664 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.3074709664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1657165578
Short name T962
Test name
Test status
Simulation time 64774513 ps
CPU time 1.75 seconds
Started Oct 12 12:36:18 AM UTC 24
Finished Oct 12 12:36:20 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657
165578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.1657165578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.113248952
Short name T960
Test name
Test status
Simulation time 113471126 ps
CPU time 2.99 seconds
Started Oct 12 12:36:15 AM UTC 24
Finished Oct 12 12:36:19 AM UTC 24
Peak memory 219692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132489
52 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.113248952
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.946231555
Short name T942
Test name
Test status
Simulation time 151207764 ps
CPU time 3.07 seconds
Started Oct 12 12:36:15 AM UTC 24
Finished Oct 12 12:36:19 AM UTC 24
Peak memory 219628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=946231555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_
errors_with_csr_rw.946231555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.3784495924
Short name T921
Test name
Test status
Simulation time 26911151 ps
CPU time 2.54 seconds
Started Oct 12 12:36:16 AM UTC 24
Finished Oct 12 12:36:20 AM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784495924 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.3784495924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1243605078
Short name T967
Test name
Test status
Simulation time 367998963 ps
CPU time 5.49 seconds
Started Oct 12 12:36:17 AM UTC 24
Finished Oct 12 12:36:23 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243605078 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.1243605078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2649546352
Short name T971
Test name
Test status
Simulation time 40654914 ps
CPU time 2.12 seconds
Started Oct 12 12:36:21 AM UTC 24
Finished Oct 12 12:36:25 AM UTC 24
Peak memory 210144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2649546352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_csr_mem_rw_with_rand_reset.2649546352
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.1059904011
Short name T968
Test name
Test status
Simulation time 20106788 ps
CPU time 1.22 seconds
Started Oct 12 12:36:21 AM UTC 24
Finished Oct 12 12:36:23 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059904011 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.1059904011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.3341836406
Short name T965
Test name
Test status
Simulation time 37633609 ps
CPU time 1.19 seconds
Started Oct 12 12:36:20 AM UTC 24
Finished Oct 12 12:36:22 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341836406 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.3341836406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3814733290
Short name T970
Test name
Test status
Simulation time 24626173 ps
CPU time 1.54 seconds
Started Oct 12 12:36:21 AM UTC 24
Finished Oct 12 12:36:24 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814
733290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.3814733290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1026530606
Short name T966
Test name
Test status
Simulation time 285182387 ps
CPU time 2.78 seconds
Started Oct 12 12:36:19 AM UTC 24
Finished Oct 12 12:36:23 AM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026530
606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.1026530606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2883836274
Short name T972
Test name
Test status
Simulation time 599070220 ps
CPU time 4.21 seconds
Started Oct 12 12:36:20 AM UTC 24
Finished Oct 12 12:36:25 AM UTC 24
Peak memory 219628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2883836274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg
_errors_with_csr_rw.2883836274
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3176840503
Short name T973
Test name
Test status
Simulation time 227844331 ps
CPU time 4.37 seconds
Started Oct 12 12:36:20 AM UTC 24
Finished Oct 12 12:36:25 AM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176840503 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.3176840503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2353009962
Short name T969
Test name
Test status
Simulation time 70137079 ps
CPU time 2.41 seconds
Started Oct 12 12:36:20 AM UTC 24
Finished Oct 12 12:36:24 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353009962 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.2353009962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3720271110
Short name T982
Test name
Test status
Simulation time 82884513 ps
CPU time 1.72 seconds
Started Oct 12 12:36:25 AM UTC 24
Finished Oct 12 12:36:27 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3720271110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_csr_mem_rw_with_rand_reset.3720271110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.1510873707
Short name T975
Test name
Test status
Simulation time 48505147 ps
CPU time 1.39 seconds
Started Oct 12 12:36:24 AM UTC 24
Finished Oct 12 12:36:26 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510873707 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.1510873707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.539017547
Short name T974
Test name
Test status
Simulation time 13753989 ps
CPU time 1.13 seconds
Started Oct 12 12:36:23 AM UTC 24
Finished Oct 12 12:36:26 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539017547 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.539017547
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1414045497
Short name T981
Test name
Test status
Simulation time 52323146 ps
CPU time 1.57 seconds
Started Oct 12 12:36:25 AM UTC 24
Finished Oct 12 12:36:27 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414
045497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.1414045497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.367542801
Short name T149
Test name
Test status
Simulation time 48011697 ps
CPU time 1.4 seconds
Started Oct 12 12:36:21 AM UTC 24
Finished Oct 12 12:36:24 AM UTC 24
Peak memory 209416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675428
01 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.367542801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.117736201
Short name T144
Test name
Test status
Simulation time 381523210 ps
CPU time 3.86 seconds
Started Oct 12 12:36:23 AM UTC 24
Finished Oct 12 12:36:28 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=117736201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_
errors_with_csr_rw.117736201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.2866785833
Short name T976
Test name
Test status
Simulation time 159762884 ps
CPU time 2.32 seconds
Started Oct 12 12:36:23 AM UTC 24
Finished Oct 12 12:36:27 AM UTC 24
Peak memory 210088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866785833 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.2866785833
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.294410976
Short name T977
Test name
Test status
Simulation time 76936893 ps
CPU time 2.33 seconds
Started Oct 12 12:36:23 AM UTC 24
Finished Oct 12 12:36:27 AM UTC 24
Peak memory 210160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294410976 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.294410976
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.740826354
Short name T88
Test name
Test status
Simulation time 90675513 ps
CPU time 2.33 seconds
Started Oct 12 12:35:10 AM UTC 24
Finished Oct 12 12:35:13 AM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740826354 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.740826354
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2053373778
Short name T874
Test name
Test status
Simulation time 261326787 ps
CPU time 7.37 seconds
Started Oct 12 12:35:10 AM UTC 24
Finished Oct 12 12:35:18 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053373778 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.2053373778
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.544325922
Short name T867
Test name
Test status
Simulation time 49635126 ps
CPU time 1.38 seconds
Started Oct 12 12:35:05 AM UTC 24
Finished Oct 12 12:35:08 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544325922 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.544325922
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3582808203
Short name T869
Test name
Test status
Simulation time 41593201 ps
CPU time 1.88 seconds
Started Oct 12 12:35:11 AM UTC 24
Finished Oct 12 12:35:14 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3582808203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.clkmgr_csr_mem_rw_with_rand_reset.3582808203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.3844383181
Short name T868
Test name
Test status
Simulation time 50908913 ps
CPU time 1.34 seconds
Started Oct 12 12:35:10 AM UTC 24
Finished Oct 12 12:35:12 AM UTC 24
Peak memory 209892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844383181 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.3844383181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.808780972
Short name T866
Test name
Test status
Simulation time 37207741 ps
CPU time 1.1 seconds
Started Oct 12 12:35:04 AM UTC 24
Finished Oct 12 12:35:07 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808780972 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.808780972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.461868919
Short name T89
Test name
Test status
Simulation time 76205631 ps
CPU time 1.95 seconds
Started Oct 12 12:35:11 AM UTC 24
Finished Oct 12 12:35:14 AM UTC 24
Peak memory 209484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4618
68919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.461868919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1421067069
Short name T113
Test name
Test status
Simulation time 164675039 ps
CPU time 3.43 seconds
Started Oct 12 12:34:59 AM UTC 24
Finished Oct 12 12:35:04 AM UTC 24
Peak memory 226712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421067
069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.1421067069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1689340121
Short name T87
Test name
Test status
Simulation time 87632755 ps
CPU time 3.02 seconds
Started Oct 12 12:35:00 AM UTC 24
Finished Oct 12 12:35:04 AM UTC 24
Peak memory 219700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1689340121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_
errors_with_csr_rw.1689340121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.1726978276
Short name T864
Test name
Test status
Simulation time 100708665 ps
CPU time 4.17 seconds
Started Oct 12 12:35:00 AM UTC 24
Finished Oct 12 12:35:05 AM UTC 24
Peak memory 210120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726978276 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.1726978276
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1895916313
Short name T118
Test name
Test status
Simulation time 120866631 ps
CPU time 4.51 seconds
Started Oct 12 12:35:00 AM UTC 24
Finished Oct 12 12:35:06 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895916313 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.1895916313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.1234802514
Short name T978
Test name
Test status
Simulation time 12390412 ps
CPU time 1.01 seconds
Started Oct 12 12:36:25 AM UTC 24
Finished Oct 12 12:36:27 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234802514 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.1234802514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.2410240882
Short name T980
Test name
Test status
Simulation time 28038006 ps
CPU time 1.02 seconds
Started Oct 12 12:36:25 AM UTC 24
Finished Oct 12 12:36:27 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410240882 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.2410240882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.1845301076
Short name T979
Test name
Test status
Simulation time 37843386 ps
CPU time 0.93 seconds
Started Oct 12 12:36:25 AM UTC 24
Finished Oct 12 12:36:27 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845301076 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.1845301076
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.449019152
Short name T986
Test name
Test status
Simulation time 21218785 ps
CPU time 1.16 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:33 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449019152 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.449019152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.2729375057
Short name T983
Test name
Test status
Simulation time 14647603 ps
CPU time 0.95 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:33 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729375057 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.2729375057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.2457268534
Short name T985
Test name
Test status
Simulation time 23739824 ps
CPU time 1.05 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:33 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457268534 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.2457268534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.2975119160
Short name T988
Test name
Test status
Simulation time 17826210 ps
CPU time 1.04 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:33 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975119160 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.2975119160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.4281416365
Short name T984
Test name
Test status
Simulation time 12630842 ps
CPU time 0.93 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:33 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281416365 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.4281416365
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.1069497043
Short name T987
Test name
Test status
Simulation time 13873909 ps
CPU time 0.94 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:33 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069497043 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.1069497043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.2181681033
Short name T989
Test name
Test status
Simulation time 10916503 ps
CPU time 0.96 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:33 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181681033 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.2181681033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1748915014
Short name T875
Test name
Test status
Simulation time 119208385 ps
CPU time 2.04 seconds
Started Oct 12 12:35:18 AM UTC 24
Finished Oct 12 12:35:21 AM UTC 24
Peak memory 209944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748915014 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.1748915014
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3012341469
Short name T882
Test name
Test status
Simulation time 3229073318 ps
CPU time 16.96 seconds
Started Oct 12 12:35:18 AM UTC 24
Finished Oct 12 12:35:36 AM UTC 24
Peak memory 210284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012341469 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.3012341469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.967590491
Short name T871
Test name
Test status
Simulation time 26216289 ps
CPU time 1.23 seconds
Started Oct 12 12:35:14 AM UTC 24
Finished Oct 12 12:35:17 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967590491 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.967590491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2820167514
Short name T876
Test name
Test status
Simulation time 44489819 ps
CPU time 1.49 seconds
Started Oct 12 12:35:19 AM UTC 24
Finished Oct 12 12:35:21 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2820167514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_csr_mem_rw_with_rand_reset.2820167514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.1095239270
Short name T873
Test name
Test status
Simulation time 80251712 ps
CPU time 1.35 seconds
Started Oct 12 12:35:15 AM UTC 24
Finished Oct 12 12:35:18 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095239270 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.1095239270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.2354795233
Short name T870
Test name
Test status
Simulation time 29404897 ps
CPU time 1.1 seconds
Started Oct 12 12:35:14 AM UTC 24
Finished Oct 12 12:35:16 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354795233 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.2354795233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3195240940
Short name T877
Test name
Test status
Simulation time 73983814 ps
CPU time 1.88 seconds
Started Oct 12 12:35:19 AM UTC 24
Finished Oct 12 12:35:22 AM UTC 24
Peak memory 209540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195
240940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.3195240940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1094288610
Short name T90
Test name
Test status
Simulation time 99342156 ps
CPU time 3.2 seconds
Started Oct 12 12:35:13 AM UTC 24
Finished Oct 12 12:35:17 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1094288610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_
errors_with_csr_rw.1094288610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.1393138054
Short name T872
Test name
Test status
Simulation time 109395132 ps
CPU time 3.54 seconds
Started Oct 12 12:35:13 AM UTC 24
Finished Oct 12 12:35:18 AM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393138054 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.1393138054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.1711138097
Short name T991
Test name
Test status
Simulation time 12052843 ps
CPU time 0.99 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711138097 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.1711138097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.2663562334
Short name T993
Test name
Test status
Simulation time 30108649 ps
CPU time 1.13 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663562334 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.2663562334
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.1700098891
Short name T992
Test name
Test status
Simulation time 12902091 ps
CPU time 0.97 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700098891 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.1700098891
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.4030422163
Short name T990
Test name
Test status
Simulation time 15459179 ps
CPU time 0.89 seconds
Started Oct 12 12:36:31 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030422163 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.4030422163
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.3013480153
Short name T998
Test name
Test status
Simulation time 64223674 ps
CPU time 1.28 seconds
Started Oct 12 12:36:32 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013480153 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.3013480153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.3772201995
Short name T996
Test name
Test status
Simulation time 37380453 ps
CPU time 1.07 seconds
Started Oct 12 12:36:32 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772201995 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.3772201995
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.989537044
Short name T997
Test name
Test status
Simulation time 26003675 ps
CPU time 1.02 seconds
Started Oct 12 12:36:32 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989537044 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.989537044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.3476829810
Short name T994
Test name
Test status
Simulation time 15956417 ps
CPU time 0.95 seconds
Started Oct 12 12:36:32 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476829810 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.3476829810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.893490575
Short name T995
Test name
Test status
Simulation time 11412756 ps
CPU time 0.87 seconds
Started Oct 12 12:36:32 AM UTC 24
Finished Oct 12 12:36:34 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893490575 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.893490575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.3146207364
Short name T999
Test name
Test status
Simulation time 23586422 ps
CPU time 1.1 seconds
Started Oct 12 12:36:34 AM UTC 24
Finished Oct 12 12:36:36 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146207364 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.3146207364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3959207384
Short name T887
Test name
Test status
Simulation time 140543499 ps
CPU time 3.33 seconds
Started Oct 12 12:35:34 AM UTC 24
Finished Oct 12 12:35:39 AM UTC 24
Peak memory 210092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959207384 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.3959207384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.55493854
Short name T885
Test name
Test status
Simulation time 352598262 ps
CPU time 4.86 seconds
Started Oct 12 12:35:32 AM UTC 24
Finished Oct 12 12:35:38 AM UTC 24
Peak memory 210072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55493854 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.55493854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2978845394
Short name T880
Test name
Test status
Simulation time 28875153 ps
CPU time 1.22 seconds
Started Oct 12 12:35:22 AM UTC 24
Finished Oct 12 12:35:24 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978845394 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.2978845394
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3447011007
Short name T883
Test name
Test status
Simulation time 103305820 ps
CPU time 1.54 seconds
Started Oct 12 12:35:35 AM UTC 24
Finished Oct 12 12:35:37 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3447011007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.clkmgr_csr_mem_rw_with_rand_reset.3447011007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.1349375690
Short name T881
Test name
Test status
Simulation time 17289433 ps
CPU time 1.39 seconds
Started Oct 12 12:35:32 AM UTC 24
Finished Oct 12 12:35:35 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349375690 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.1349375690
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.1702021950
Short name T879
Test name
Test status
Simulation time 25691012 ps
CPU time 1.04 seconds
Started Oct 12 12:35:22 AM UTC 24
Finished Oct 12 12:35:24 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702021950 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.1702021950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3636768115
Short name T886
Test name
Test status
Simulation time 122858604 ps
CPU time 2.86 seconds
Started Oct 12 12:35:34 AM UTC 24
Finished Oct 12 12:35:38 AM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636
768115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.3636768115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2033943057
Short name T115
Test name
Test status
Simulation time 238643251 ps
CPU time 4.19 seconds
Started Oct 12 12:35:19 AM UTC 24
Finished Oct 12 12:35:24 AM UTC 24
Peak memory 226740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033943
057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.2033943057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2979700003
Short name T138
Test name
Test status
Simulation time 246131520 ps
CPU time 4.1 seconds
Started Oct 12 12:35:19 AM UTC 24
Finished Oct 12 12:35:24 AM UTC 24
Peak memory 219764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2979700003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_
errors_with_csr_rw.2979700003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.2858948807
Short name T878
Test name
Test status
Simulation time 60578568 ps
CPU time 1.88 seconds
Started Oct 12 12:35:21 AM UTC 24
Finished Oct 12 12:35:24 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858948807 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.2858948807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1852076095
Short name T127
Test name
Test status
Simulation time 153239980 ps
CPU time 2.37 seconds
Started Oct 12 12:35:21 AM UTC 24
Finished Oct 12 12:35:25 AM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852076095 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.1852076095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.1069943892
Short name T1000
Test name
Test status
Simulation time 12125371 ps
CPU time 0.99 seconds
Started Oct 12 12:36:34 AM UTC 24
Finished Oct 12 12:36:36 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069943892 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.1069943892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.2014578032
Short name T1002
Test name
Test status
Simulation time 12496382 ps
CPU time 1.1 seconds
Started Oct 12 12:36:34 AM UTC 24
Finished Oct 12 12:36:36 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014578032 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.2014578032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.2176868762
Short name T1001
Test name
Test status
Simulation time 27065028 ps
CPU time 1.13 seconds
Started Oct 12 12:36:34 AM UTC 24
Finished Oct 12 12:36:36 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176868762 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.2176868762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.2045072529
Short name T1003
Test name
Test status
Simulation time 14296432 ps
CPU time 1.12 seconds
Started Oct 12 12:36:34 AM UTC 24
Finished Oct 12 12:36:36 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045072529 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.2045072529
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.4156618118
Short name T1005
Test name
Test status
Simulation time 97268243 ps
CPU time 1.33 seconds
Started Oct 12 12:36:34 AM UTC 24
Finished Oct 12 12:36:37 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156618118 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.4156618118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.2358992915
Short name T1004
Test name
Test status
Simulation time 39918855 ps
CPU time 1.14 seconds
Started Oct 12 12:36:34 AM UTC 24
Finished Oct 12 12:36:37 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358992915 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.2358992915
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.1127464731
Short name T1006
Test name
Test status
Simulation time 20050728 ps
CPU time 1.03 seconds
Started Oct 12 12:36:35 AM UTC 24
Finished Oct 12 12:36:37 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127464731 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.1127464731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.1928232689
Short name T1007
Test name
Test status
Simulation time 14947315 ps
CPU time 1.05 seconds
Started Oct 12 12:36:35 AM UTC 24
Finished Oct 12 12:36:37 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928232689 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.1928232689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.3044343221
Short name T1008
Test name
Test status
Simulation time 12625241 ps
CPU time 1.05 seconds
Started Oct 12 12:36:36 AM UTC 24
Finished Oct 12 12:36:38 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044343221 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.3044343221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1415129902
Short name T1009
Test name
Test status
Simulation time 12211757 ps
CPU time 0.98 seconds
Started Oct 12 12:36:36 AM UTC 24
Finished Oct 12 12:36:38 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415129902 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.1415129902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.4244179594
Short name T891
Test name
Test status
Simulation time 95652291 ps
CPU time 1.95 seconds
Started Oct 12 12:35:39 AM UTC 24
Finished Oct 12 12:35:42 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4244179594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_csr_mem_rw_with_rand_reset.4244179594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.3844776367
Short name T888
Test name
Test status
Simulation time 26359577 ps
CPU time 1.17 seconds
Started Oct 12 12:35:37 AM UTC 24
Finished Oct 12 12:35:39 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844776367 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.3844776367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.3890235589
Short name T884
Test name
Test status
Simulation time 12178311 ps
CPU time 1.02 seconds
Started Oct 12 12:35:36 AM UTC 24
Finished Oct 12 12:35:38 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890235589 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.3890235589
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2706058522
Short name T889
Test name
Test status
Simulation time 63849324 ps
CPU time 2.16 seconds
Started Oct 12 12:35:38 AM UTC 24
Finished Oct 12 12:35:41 AM UTC 24
Peak memory 210060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706
058522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.2706058522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.715133169
Short name T145
Test name
Test status
Simulation time 83981461 ps
CPU time 2.57 seconds
Started Oct 12 12:35:35 AM UTC 24
Finished Oct 12 12:35:38 AM UTC 24
Peak memory 210208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7151331
69 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.715133169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.4094100288
Short name T146
Test name
Test status
Simulation time 115585878 ps
CPU time 4.42 seconds
Started Oct 12 12:35:35 AM UTC 24
Finished Oct 12 12:35:40 AM UTC 24
Peak memory 219700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4094100288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_
errors_with_csr_rw.4094100288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.4060187677
Short name T890
Test name
Test status
Simulation time 420107868 ps
CPU time 6.06 seconds
Started Oct 12 12:35:35 AM UTC 24
Finished Oct 12 12:35:42 AM UTC 24
Peak memory 210064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060187677 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.4060187677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2002332742
Short name T129
Test name
Test status
Simulation time 67629175 ps
CPU time 2.94 seconds
Started Oct 12 12:35:35 AM UTC 24
Finished Oct 12 12:35:39 AM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002332742 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.2002332742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3681101357
Short name T897
Test name
Test status
Simulation time 238382985 ps
CPU time 2.22 seconds
Started Oct 12 12:35:43 AM UTC 24
Finished Oct 12 12:35:46 AM UTC 24
Peak memory 210084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3681101357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_csr_mem_rw_with_rand_reset.3681101357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.1727337846
Short name T893
Test name
Test status
Simulation time 26405590 ps
CPU time 1.18 seconds
Started Oct 12 12:35:41 AM UTC 24
Finished Oct 12 12:35:43 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727337846 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.1727337846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.176426081
Short name T892
Test name
Test status
Simulation time 33625652 ps
CPU time 1.07 seconds
Started Oct 12 12:35:40 AM UTC 24
Finished Oct 12 12:35:43 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176426081 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.176426081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2702138216
Short name T895
Test name
Test status
Simulation time 60422741 ps
CPU time 1.44 seconds
Started Oct 12 12:35:42 AM UTC 24
Finished Oct 12 12:35:44 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702
138216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.2702138216
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1408465403
Short name T143
Test name
Test status
Simulation time 75175147 ps
CPU time 1.68 seconds
Started Oct 12 12:35:39 AM UTC 24
Finished Oct 12 12:35:42 AM UTC 24
Peak memory 209360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408465
403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.1408465403
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.201372305
Short name T139
Test name
Test status
Simulation time 100583734 ps
CPU time 3.09 seconds
Started Oct 12 12:35:39 AM UTC 24
Finished Oct 12 12:35:44 AM UTC 24
Peak memory 219624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=201372305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_e
rrors_with_csr_rw.201372305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.2813618638
Short name T896
Test name
Test status
Simulation time 251835409 ps
CPU time 4.54 seconds
Started Oct 12 12:35:39 AM UTC 24
Finished Oct 12 12:35:45 AM UTC 24
Peak memory 210260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813618638 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.2813618638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2233525324
Short name T894
Test name
Test status
Simulation time 140777307 ps
CPU time 2.93 seconds
Started Oct 12 12:35:39 AM UTC 24
Finished Oct 12 12:35:44 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233525324 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.2233525324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2829445321
Short name T901
Test name
Test status
Simulation time 27697787 ps
CPU time 1.5 seconds
Started Oct 12 12:35:45 AM UTC 24
Finished Oct 12 12:35:48 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2829445321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.clkmgr_csr_mem_rw_with_rand_reset.2829445321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.1791642652
Short name T900
Test name
Test status
Simulation time 38420304 ps
CPU time 1.37 seconds
Started Oct 12 12:35:45 AM UTC 24
Finished Oct 12 12:35:47 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791642652 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.1791642652
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.492844493
Short name T899
Test name
Test status
Simulation time 21129385 ps
CPU time 1.12 seconds
Started Oct 12 12:35:45 AM UTC 24
Finished Oct 12 12:35:47 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492844493 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.492844493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1564983416
Short name T905
Test name
Test status
Simulation time 358803155 ps
CPU time 3.23 seconds
Started Oct 12 12:35:45 AM UTC 24
Finished Oct 12 12:35:49 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564
983416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.1564983416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1469804011
Short name T140
Test name
Test status
Simulation time 109814207 ps
CPU time 2.18 seconds
Started Oct 12 12:35:43 AM UTC 24
Finished Oct 12 12:35:46 AM UTC 24
Peak memory 219756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469804
011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.1469804011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.993804224
Short name T898
Test name
Test status
Simulation time 59646638 ps
CPU time 2.29 seconds
Started Oct 12 12:35:43 AM UTC 24
Finished Oct 12 12:35:46 AM UTC 24
Peak memory 219696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=993804224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_e
rrors_with_csr_rw.993804224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.2010041870
Short name T906
Test name
Test status
Simulation time 64612839 ps
CPU time 3.54 seconds
Started Oct 12 12:35:45 AM UTC 24
Finished Oct 12 12:35:49 AM UTC 24
Peak memory 210124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010041870 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.2010041870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1437334395
Short name T902
Test name
Test status
Simulation time 216006209 ps
CPU time 3 seconds
Started Oct 12 12:35:45 AM UTC 24
Finished Oct 12 12:35:49 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437334395 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.1437334395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2329587969
Short name T909
Test name
Test status
Simulation time 93544570 ps
CPU time 1.8 seconds
Started Oct 12 12:35:49 AM UTC 24
Finished Oct 12 12:35:51 AM UTC 24
Peak memory 209476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2329587969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_csr_mem_rw_with_rand_reset.2329587969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.1749558236
Short name T903
Test name
Test status
Simulation time 21497013 ps
CPU time 1.28 seconds
Started Oct 12 12:35:48 AM UTC 24
Finished Oct 12 12:35:51 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749558236 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.1749558236
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.3012623405
Short name T904
Test name
Test status
Simulation time 26065337 ps
CPU time 1.04 seconds
Started Oct 12 12:35:47 AM UTC 24
Finished Oct 12 12:35:49 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012623405 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.3012623405
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1098460326
Short name T910
Test name
Test status
Simulation time 52284435 ps
CPU time 1.95 seconds
Started Oct 12 12:35:49 AM UTC 24
Finished Oct 12 12:35:51 AM UTC 24
Peak memory 209540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098
460326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.1098460326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3446609741
Short name T141
Test name
Test status
Simulation time 486481247 ps
CPU time 3.91 seconds
Started Oct 12 12:35:45 AM UTC 24
Finished Oct 12 12:35:50 AM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446609
741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.3446609741
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1598956884
Short name T147
Test name
Test status
Simulation time 76799803 ps
CPU time 2.15 seconds
Started Oct 12 12:35:46 AM UTC 24
Finished Oct 12 12:35:49 AM UTC 24
Peak memory 219764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1598956884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_
errors_with_csr_rw.1598956884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.3296089875
Short name T908
Test name
Test status
Simulation time 186520179 ps
CPU time 2.74 seconds
Started Oct 12 12:35:47 AM UTC 24
Finished Oct 12 12:35:51 AM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296089875 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.3296089875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3830021985
Short name T907
Test name
Test status
Simulation time 88575277 ps
CPU time 2.37 seconds
Started Oct 12 12:35:47 AM UTC 24
Finished Oct 12 12:35:51 AM UTC 24
Peak memory 210096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830021985 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.3830021985
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1898499701
Short name T913
Test name
Test status
Simulation time 180783317 ps
CPU time 2.47 seconds
Started Oct 12 12:35:52 AM UTC 24
Finished Oct 12 12:35:56 AM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1898499701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.clkmgr_csr_mem_rw_with_rand_reset.1898499701
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.2225686039
Short name T912
Test name
Test status
Simulation time 56098346 ps
CPU time 1.37 seconds
Started Oct 12 12:35:51 AM UTC 24
Finished Oct 12 12:35:53 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225686039 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.2225686039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.2480997843
Short name T911
Test name
Test status
Simulation time 13371046 ps
CPU time 1.02 seconds
Started Oct 12 12:35:51 AM UTC 24
Finished Oct 12 12:35:53 AM UTC 24
Peak memory 208924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480997843 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.2480997843
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3147136216
Short name T914
Test name
Test status
Simulation time 187023657 ps
CPU time 2.61 seconds
Started Oct 12 12:35:52 AM UTC 24
Finished Oct 12 12:35:56 AM UTC 24
Peak memory 210024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147
136216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.3147136216
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.939172494
Short name T153
Test name
Test status
Simulation time 260052671 ps
CPU time 2.63 seconds
Started Oct 12 12:35:50 AM UTC 24
Finished Oct 12 12:35:53 AM UTC 24
Peak memory 210552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9391724
94 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.939172494
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.4219559314
Short name T148
Test name
Test status
Simulation time 250500728 ps
CPU time 4.39 seconds
Started Oct 12 12:35:51 AM UTC 24
Finished Oct 12 12:35:56 AM UTC 24
Peak memory 219760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4219559314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_
errors_with_csr_rw.4219559314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.809419551
Short name T917
Test name
Test status
Simulation time 451890036 ps
CPU time 4.88 seconds
Started Oct 12 12:35:51 AM UTC 24
Finished Oct 12 12:35:57 AM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809419551 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.809419551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.2469125893
Short name T54
Test name
Test status
Simulation time 38195945 ps
CPU time 0.81 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469125893 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.2469125893
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.1626124737
Short name T28
Test name
Test status
Simulation time 60725215 ps
CPU time 0.93 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626124737 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.1626124737
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2825589146
Short name T24
Test name
Test status
Simulation time 14822340 ps
CPU time 0.76 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825589146
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.2825589146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.3546462800
Short name T5
Test name
Test status
Simulation time 17471445 ps
CPU time 0.75 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546462800 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3546462800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.2602559678
Short name T6
Test name
Test status
Simulation time 67466012 ps
CPU time 0.96 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602559678 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2602559678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.256948421
Short name T267
Test name
Test status
Simulation time 4380125379 ps
CPU time 23.49 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:53:12 AM UTC 24
Peak memory 211808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256948421 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.256948421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.188697042
Short name T60
Test name
Test status
Simulation time 6708092675 ps
CPU time 57.2 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 221476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188697042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.188697042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.501492215
Short name T27
Test name
Test status
Simulation time 44446796 ps
CPU time 0.91 seconds
Started Oct 12 12:52:46 AM UTC 24
Finished Oct 12 12:52:48 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501492215 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.501492215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.3791723860
Short name T100
Test name
Test status
Simulation time 37415863 ps
CPU time 0.78 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791723860 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.3791723860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3237486302
Short name T79
Test name
Test status
Simulation time 14903877 ps
CPU time 0.75 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237486302 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.3237486302
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.2077335638
Short name T76
Test name
Test status
Simulation time 65017398 ps
CPU time 0.77 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077335638 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2077335638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.2318048532
Short name T133
Test name
Test status
Simulation time 105188924 ps
CPU time 1.02 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318048532 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.2318048532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.3250631490
Short name T134
Test name
Test status
Simulation time 45303777 ps
CPU time 1.34 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250631490 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3250631490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.1458030134
Short name T3
Test name
Test status
Simulation time 573985713 ps
CPU time 2.93 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:51 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458030134 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1458030134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.1365762592
Short name T45
Test name
Test status
Simulation time 2351163723 ps
CPU time 10.07 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365762592 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.1365762592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.3049559903
Short name T135
Test name
Test status
Simulation time 27116784 ps
CPU time 0.91 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049559903 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.3049559903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2836110691
Short name T132
Test name
Test status
Simulation time 13456286 ps
CPU time 0.76 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836110691
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.2836110691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3718942934
Short name T75
Test name
Test status
Simulation time 15092289 ps
CPU time 0.71 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718942934
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.3718942934
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.2232288714
Short name T74
Test name
Test status
Simulation time 15559849 ps
CPU time 0.7 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232288714 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2232288714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.2353807442
Short name T2
Test name
Test status
Simulation time 275366340 ps
CPU time 1.97 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:50 AM UTC 24
Peak memory 211492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353807442 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2353807442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.3295164416
Short name T16
Test name
Test status
Simulation time 139878673 ps
CPU time 1.74 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:50 AM UTC 24
Peak memory 243752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295164416 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.3295164416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.2680985960
Short name T56
Test name
Test status
Simulation time 2244362793 ps
CPU time 39.87 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:53:29 AM UTC 24
Peak memory 221676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680985960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.2680985960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.283295886
Short name T78
Test name
Test status
Simulation time 26723962 ps
CPU time 0.8 seconds
Started Oct 12 12:52:47 AM UTC 24
Finished Oct 12 12:52:49 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283295886 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.283295886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.3327033765
Short name T270
Test name
Test status
Simulation time 39068023 ps
CPU time 0.92 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:13 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327033765 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.3327033765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.179465333
Short name T264
Test name
Test status
Simulation time 39769864 ps
CPU time 1 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179465333 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.179465333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.545939562
Short name T261
Test name
Test status
Simulation time 14449154 ps
CPU time 0.89 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545939562 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.545939562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.3017504459
Short name T259
Test name
Test status
Simulation time 49181912 ps
CPU time 1.06 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017504459 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3017504459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.3324593324
Short name T47
Test name
Test status
Simulation time 2370056211 ps
CPU time 11.11 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:20 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324593324 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3324593324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.2051126320
Short name T104
Test name
Test status
Simulation time 385781543 ps
CPU time 2.47 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:12 AM UTC 24
Peak memory 211540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051126320 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.2051126320
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.4049434406
Short name T265
Test name
Test status
Simulation time 57329555 ps
CPU time 1.17 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049434406 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.4049434406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.606437845
Short name T266
Test name
Test status
Simulation time 19817128 ps
CPU time 1.04 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606437845 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.606437845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.353626750
Short name T262
Test name
Test status
Simulation time 50417610 ps
CPU time 0.86 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353626750 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.353626750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.3912516538
Short name T263
Test name
Test status
Simulation time 191231642 ps
CPU time 1.27 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912516538 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3912516538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.1029922065
Short name T279
Test name
Test status
Simulation time 756142159 ps
CPU time 4.21 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029922065 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.1029922065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.1752386490
Short name T158
Test name
Test status
Simulation time 67578774 ps
CPU time 0.99 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752386490 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1752386490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.111968947
Short name T423
Test name
Test status
Simulation time 6425923321 ps
CPU time 51.64 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:54:04 AM UTC 24
Peak memory 211808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111968947 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.111968947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.2535564089
Short name T58
Test name
Test status
Simulation time 1281848287 ps
CPU time 20.54 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 221432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535564089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.2535564089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.3025998181
Short name T260
Test name
Test status
Simulation time 28454925 ps
CPU time 0.93 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025998181 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.3025998181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.3211331853
Short name T278
Test name
Test status
Simulation time 53748700 ps
CPU time 1.07 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:15 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211331853 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.3211331853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.693569013
Short name T206
Test name
Test status
Simulation time 23055091 ps
CPU time 1.15 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:14 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693569013 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.693569013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.930186233
Short name T273
Test name
Test status
Simulation time 13704129 ps
CPU time 0.85 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:14 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930186233 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.930186233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.3731456027
Short name T277
Test name
Test status
Simulation time 21973477 ps
CPU time 1.07 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:14 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731456027 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.3731456027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.3081375087
Short name T258
Test name
Test status
Simulation time 25507835 ps
CPU time 0.9 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:13 AM UTC 24
Peak memory 211624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081375087 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.3081375087
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.4164294034
Short name T306
Test name
Test status
Simulation time 2021241903 ps
CPU time 9.65 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164294034 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.4164294034
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.459363348
Short name T332
Test name
Test status
Simulation time 2061158731 ps
CPU time 14.83 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:27 AM UTC 24
Peak memory 212080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459363348 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.459363348
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.775646918
Short name T274
Test name
Test status
Simulation time 25071610 ps
CPU time 0.97 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:14 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775646918 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.775646918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1570771722
Short name T275
Test name
Test status
Simulation time 20145422 ps
CPU time 1.2 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:14 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570771722
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.1570771722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1600368391
Short name T276
Test name
Test status
Simulation time 25043357 ps
CPU time 1.17 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:14 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600368391
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.1600368391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.1497543478
Short name T242
Test name
Test status
Simulation time 16680950 ps
CPU time 0.81 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:13 AM UTC 24
Peak memory 209228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497543478 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1497543478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.1035863137
Short name T131
Test name
Test status
Simulation time 526231080 ps
CPU time 2.68 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035863137 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1035863137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.359329623
Short name T233
Test name
Test status
Simulation time 46065250 ps
CPU time 1.15 seconds
Started Oct 12 12:53:11 AM UTC 24
Finished Oct 12 12:53:13 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359329623 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.359329623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.409868266
Short name T447
Test name
Test status
Simulation time 10653207511 ps
CPU time 58.72 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:54:13 AM UTC 24
Peak memory 211892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409868266 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.409868266
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.4164255652
Short name T62
Test name
Test status
Simulation time 4311951481 ps
CPU time 44.38 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:58 AM UTC 24
Peak memory 228392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164255652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.4164255652
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.146085460
Short name T271
Test name
Test status
Simulation time 20044115 ps
CPU time 0.9 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:14 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146085460 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.146085460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.3454152036
Short name T289
Test name
Test status
Simulation time 25122155 ps
CPU time 0.89 seconds
Started Oct 12 12:53:15 AM UTC 24
Finished Oct 12 12:53:17 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454152036 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.3454152036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.2706025544
Short name T291
Test name
Test status
Simulation time 440970715 ps
CPU time 2.41 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706025544 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.2706025544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.3516531367
Short name T283
Test name
Test status
Simulation time 18047018 ps
CPU time 1.13 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516531367 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3516531367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.1086552048
Short name T286
Test name
Test status
Simulation time 59596573 ps
CPU time 1.15 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086552048 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.1086552048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.1893963044
Short name T243
Test name
Test status
Simulation time 57873915 ps
CPU time 1.07 seconds
Started Oct 12 12:53:13 AM UTC 24
Finished Oct 12 12:53:15 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893963044 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1893963044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.2186770700
Short name T299
Test name
Test status
Simulation time 1044177116 ps
CPU time 6.87 seconds
Started Oct 12 12:53:13 AM UTC 24
Finished Oct 12 12:53:21 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186770700 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.2186770700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.2375475371
Short name T298
Test name
Test status
Simulation time 1352039821 ps
CPU time 6.55 seconds
Started Oct 12 12:53:13 AM UTC 24
Finished Oct 12 12:53:20 AM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375475371 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.2375475371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.4064826497
Short name T282
Test name
Test status
Simulation time 16827488 ps
CPU time 1.1 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064826497 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.4064826497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.4063955311
Short name T285
Test name
Test status
Simulation time 27735722 ps
CPU time 1.24 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063955311
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.4063955311
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1149403042
Short name T280
Test name
Test status
Simulation time 29850933 ps
CPU time 0.95 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149403042
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.1149403042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.3998010842
Short name T281
Test name
Test status
Simulation time 34054014 ps
CPU time 1.09 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998010842 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3998010842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.2809245123
Short name T287
Test name
Test status
Simulation time 375823929 ps
CPU time 1.86 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:17 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809245123 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2809245123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.4204138671
Short name T159
Test name
Test status
Simulation time 22291385 ps
CPU time 1.06 seconds
Started Oct 12 12:53:12 AM UTC 24
Finished Oct 12 12:53:15 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204138671 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.4204138671
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.1850193608
Short name T163
Test name
Test status
Simulation time 7489472957 ps
CPU time 27.24 seconds
Started Oct 12 12:53:15 AM UTC 24
Finished Oct 12 12:53:44 AM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850193608 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.1850193608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.3844578903
Short name T434
Test name
Test status
Simulation time 3119197740 ps
CPU time 52.11 seconds
Started Oct 12 12:53:15 AM UTC 24
Finished Oct 12 12:54:09 AM UTC 24
Peak memory 228344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844578903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.3844578903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.152050986
Short name T284
Test name
Test status
Simulation time 33254545 ps
CPU time 1.27 seconds
Started Oct 12 12:53:14 AM UTC 24
Finished Oct 12 12:53:16 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152050986 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.152050986
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.3468272630
Short name T317
Test name
Test status
Simulation time 18748754 ps
CPU time 1.02 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:53:23 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468272630 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.3468272630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1159386160
Short name T95
Test name
Test status
Simulation time 18134275 ps
CPU time 0.96 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159386160 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.1159386160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.3733618723
Short name T294
Test name
Test status
Simulation time 34558885 ps
CPU time 0.88 seconds
Started Oct 12 12:53:16 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733618723 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3733618723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.3405307624
Short name T310
Test name
Test status
Simulation time 23837491 ps
CPU time 0.84 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405307624 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.3405307624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.2237566718
Short name T292
Test name
Test status
Simulation time 43576695 ps
CPU time 1.03 seconds
Started Oct 12 12:53:16 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237566718 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2237566718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.1942194043
Short name T334
Test name
Test status
Simulation time 2462666820 ps
CPU time 11.59 seconds
Started Oct 12 12:53:16 AM UTC 24
Finished Oct 12 12:53:28 AM UTC 24
Peak memory 211828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942194043 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.1942194043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.1672502747
Short name T295
Test name
Test status
Simulation time 16171945 ps
CPU time 1.06 seconds
Started Oct 12 12:53:16 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672502747 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.1672502747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.3588588912
Short name T314
Test name
Test status
Simulation time 18357802 ps
CPU time 1.06 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588588912
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.3588588912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2154805941
Short name T315
Test name
Test status
Simulation time 28200703 ps
CPU time 1.17 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154805941
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.2154805941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.378255994
Short name T293
Test name
Test status
Simulation time 37316398 ps
CPU time 0.92 seconds
Started Oct 12 12:53:16 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378255994 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.378255994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.180705050
Short name T319
Test name
Test status
Simulation time 633420031 ps
CPU time 2.48 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:53:24 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180705050 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.180705050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.3113313729
Short name T160
Test name
Test status
Simulation time 23152696 ps
CPU time 1 seconds
Started Oct 12 12:53:15 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113313729 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3113313729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.3180435706
Short name T415
Test name
Test status
Simulation time 9046860019 ps
CPU time 39.81 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:54:02 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180435706 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.3180435706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.2556219045
Short name T63
Test name
Test status
Simulation time 5755942366 ps
CPU time 38.88 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556219045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.2556219045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.2643151122
Short name T296
Test name
Test status
Simulation time 41126907 ps
CPU time 1.14 seconds
Started Oct 12 12:53:16 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643151122 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2643151122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.1257514539
Short name T333
Test name
Test status
Simulation time 112203920 ps
CPU time 1.48 seconds
Started Oct 12 12:53:21 AM UTC 24
Finished Oct 12 12:53:27 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257514539 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.1257514539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3364254446
Short name T304
Test name
Test status
Simulation time 112313200 ps
CPU time 1.23 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:21 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364254446 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.3364254446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.128015346
Short name T307
Test name
Test status
Simulation time 28390452 ps
CPU time 0.84 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128015346 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.128015346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.1405928304
Short name T300
Test name
Test status
Simulation time 24380846 ps
CPU time 0.8 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:21 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405928304 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.1405928304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.905807371
Short name T313
Test name
Test status
Simulation time 201916939 ps
CPU time 1.58 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905807371 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.905807371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.349296838
Short name T66
Test name
Test status
Simulation time 1521586482 ps
CPU time 8.9 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:30 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349296838 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.349296838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.885813218
Short name T320
Test name
Test status
Simulation time 507174605 ps
CPU time 3.32 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:24 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885813218 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.885813218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.1678037368
Short name T303
Test name
Test status
Simulation time 28236296 ps
CPU time 1.09 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:21 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678037368 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.1678037368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.3230187945
Short name T301
Test name
Test status
Simulation time 23838969 ps
CPU time 0.84 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:21 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230187945
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.3230187945
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.2701092184
Short name T302
Test name
Test status
Simulation time 28787953 ps
CPU time 1.03 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:21 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701092184
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.2701092184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.2168987217
Short name T309
Test name
Test status
Simulation time 50288179 ps
CPU time 1.09 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168987217 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2168987217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.963995290
Short name T316
Test name
Test status
Simulation time 271149238 ps
CPU time 1.45 seconds
Started Oct 12 12:53:20 AM UTC 24
Finished Oct 12 12:53:23 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963995290 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.963995290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.2732734037
Short name T318
Test name
Test status
Simulation time 51923928 ps
CPU time 1.08 seconds
Started Oct 12 12:53:17 AM UTC 24
Finished Oct 12 12:53:23 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732734037 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2732734037
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.3433860445
Short name T61
Test name
Test status
Simulation time 4452465001 ps
CPU time 23.75 seconds
Started Oct 12 12:53:21 AM UTC 24
Finished Oct 12 12:53:49 AM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433860445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.3433860445
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.2744674709
Short name T312
Test name
Test status
Simulation time 109037502 ps
CPU time 1.28 seconds
Started Oct 12 12:53:19 AM UTC 24
Finished Oct 12 12:53:22 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744674709 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2744674709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.1813223841
Short name T325
Test name
Test status
Simulation time 49985543 ps
CPU time 0.87 seconds
Started Oct 12 12:53:24 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813223841 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.1813223841
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.4224543735
Short name T96
Test name
Test status
Simulation time 71665114 ps
CPU time 1.23 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224543735 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.4224543735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.3388066984
Short name T308
Test name
Test status
Simulation time 16966487 ps
CPU time 0.85 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:31 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388066984 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3388066984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.1260922101
Short name T323
Test name
Test status
Simulation time 19057058 ps
CPU time 0.97 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260922101 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.1260922101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.3852575825
Short name T331
Test name
Test status
Simulation time 72105210 ps
CPU time 1.15 seconds
Started Oct 12 12:53:21 AM UTC 24
Finished Oct 12 12:53:27 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852575825 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3852575825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.623876161
Short name T346
Test name
Test status
Simulation time 799843026 ps
CPU time 6.77 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623876161 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.623876161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.935122492
Short name T378
Test name
Test status
Simulation time 2427937106 ps
CPU time 13.25 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935122492 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.935122492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.2011897292
Short name T329
Test name
Test status
Simulation time 115122957 ps
CPU time 1.58 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011897292 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.2011897292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3012236450
Short name T339
Test name
Test status
Simulation time 145655067 ps
CPU time 1.76 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:33 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012236450
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.3012236450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.2592160543
Short name T322
Test name
Test status
Simulation time 23096429 ps
CPU time 1.04 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592160543
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.2592160543
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.434001026
Short name T290
Test name
Test status
Simulation time 40420168 ps
CPU time 1.14 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434001026 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.434001026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.3348314711
Short name T330
Test name
Test status
Simulation time 26426829 ps
CPU time 1.05 seconds
Started Oct 12 12:53:21 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348314711 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.3348314711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.1211924093
Short name T162
Test name
Test status
Simulation time 2995740365 ps
CPU time 13.51 seconds
Started Oct 12 12:53:24 AM UTC 24
Finished Oct 12 12:53:39 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211924093 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.1211924093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.187894464
Short name T457
Test name
Test status
Simulation time 3676288346 ps
CPU time 52.31 seconds
Started Oct 12 12:53:24 AM UTC 24
Finished Oct 12 12:54:18 AM UTC 24
Peak memory 221424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187894464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.187894464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.970653408
Short name T311
Test name
Test status
Simulation time 19228006 ps
CPU time 0.92 seconds
Started Oct 12 12:53:23 AM UTC 24
Finished Oct 12 12:53:31 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970653408 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.970653408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.2994303202
Short name T288
Test name
Test status
Simulation time 52238878 ps
CPU time 0.93 seconds
Started Oct 12 12:53:28 AM UTC 24
Finished Oct 12 12:53:31 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994303202 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.2994303202
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.2227861764
Short name T338
Test name
Test status
Simulation time 137230071 ps
CPU time 1.67 seconds
Started Oct 12 12:53:27 AM UTC 24
Finished Oct 12 12:53:33 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227861764 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.2227861764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.1934364861
Short name T71
Test name
Test status
Simulation time 47233846 ps
CPU time 1.17 seconds
Started Oct 12 12:53:27 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934364861 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1934364861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.2372897867
Short name T68
Test name
Test status
Simulation time 79393140 ps
CPU time 1.34 seconds
Started Oct 12 12:53:28 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372897867 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.2372897867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.4219667902
Short name T327
Test name
Test status
Simulation time 13953108 ps
CPU time 0.86 seconds
Started Oct 12 12:53:24 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219667902 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.4219667902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.2879234124
Short name T383
Test name
Test status
Simulation time 1637037440 ps
CPU time 13.99 seconds
Started Oct 12 12:53:25 AM UTC 24
Finished Oct 12 12:53:44 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879234124 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.2879234124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.1383925806
Short name T340
Test name
Test status
Simulation time 639560244 ps
CPU time 3.53 seconds
Started Oct 12 12:53:25 AM UTC 24
Finished Oct 12 12:53:33 AM UTC 24
Peak memory 211804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383925806 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.1383925806
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.2287720505
Short name T70
Test name
Test status
Simulation time 82103416 ps
CPU time 1.2 seconds
Started Oct 12 12:53:27 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287720505 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.2287720505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2056118832
Short name T335
Test name
Test status
Simulation time 59480226 ps
CPU time 1.23 seconds
Started Oct 12 12:53:27 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056118832
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.2056118832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.147350690
Short name T69
Test name
Test status
Simulation time 18438856 ps
CPU time 0.84 seconds
Started Oct 12 12:53:27 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147350690 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.147350690
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.3273429842
Short name T324
Test name
Test status
Simulation time 44250490 ps
CPU time 1.05 seconds
Started Oct 12 12:53:27 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273429842 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3273429842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.2443068542
Short name T173
Test name
Test status
Simulation time 1116182451 ps
CPU time 6.84 seconds
Started Oct 12 12:53:28 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443068542 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.2443068542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.3047600169
Short name T328
Test name
Test status
Simulation time 15450423 ps
CPU time 1.03 seconds
Started Oct 12 12:53:24 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047600169 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3047600169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.3513476630
Short name T369
Test name
Test status
Simulation time 2138316242 ps
CPU time 11.63 seconds
Started Oct 12 12:53:28 AM UTC 24
Finished Oct 12 12:53:42 AM UTC 24
Peak memory 212088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513476630 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.3513476630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.1298452870
Short name T187
Test name
Test status
Simulation time 12577689183 ps
CPU time 106.49 seconds
Started Oct 12 12:53:28 AM UTC 24
Finished Oct 12 12:55:18 AM UTC 24
Peak memory 228336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298452870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.1298452870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.3186840968
Short name T326
Test name
Test status
Simulation time 109782853 ps
CPU time 1.24 seconds
Started Oct 12 12:53:27 AM UTC 24
Finished Oct 12 12:53:32 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186840968 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3186840968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.1778186096
Short name T348
Test name
Test status
Simulation time 35156024 ps
CPU time 0.94 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778186096 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.1778186096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.691689846
Short name T351
Test name
Test status
Simulation time 21422563 ps
CPU time 1.21 seconds
Started Oct 12 12:53:34 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691689846 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.691689846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.695691025
Short name T342
Test name
Test status
Simulation time 75434891 ps
CPU time 1.06 seconds
Started Oct 12 12:53:32 AM UTC 24
Finished Oct 12 12:53:34 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695691025 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.695691025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.2082750924
Short name T347
Test name
Test status
Simulation time 19997071 ps
CPU time 1.14 seconds
Started Oct 12 12:53:34 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082750924 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.2082750924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.3524840791
Short name T336
Test name
Test status
Simulation time 27146358 ps
CPU time 1 seconds
Started Oct 12 12:53:31 AM UTC 24
Finished Oct 12 12:53:33 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524840791 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3524840791
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.3872350086
Short name T358
Test name
Test status
Simulation time 924214231 ps
CPU time 6.54 seconds
Started Oct 12 12:53:31 AM UTC 24
Finished Oct 12 12:53:38 AM UTC 24
Peak memory 211784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872350086 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3872350086
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.817252464
Short name T359
Test name
Test status
Simulation time 862733202 ps
CPU time 6.12 seconds
Started Oct 12 12:53:32 AM UTC 24
Finished Oct 12 12:53:39 AM UTC 24
Peak memory 211456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817252464 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.817252464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.3962313563
Short name T343
Test name
Test status
Simulation time 20114765 ps
CPU time 1.14 seconds
Started Oct 12 12:53:32 AM UTC 24
Finished Oct 12 12:53:35 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962313563 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.3962313563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2721742322
Short name T345
Test name
Test status
Simulation time 61943590 ps
CPU time 1.45 seconds
Started Oct 12 12:53:32 AM UTC 24
Finished Oct 12 12:53:35 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721742322
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.2721742322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1594058888
Short name T207
Test name
Test status
Simulation time 40779325 ps
CPU time 1.36 seconds
Started Oct 12 12:53:32 AM UTC 24
Finished Oct 12 12:53:35 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594058888
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.1594058888
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.2274275767
Short name T341
Test name
Test status
Simulation time 17746316 ps
CPU time 1.16 seconds
Started Oct 12 12:53:32 AM UTC 24
Finished Oct 12 12:53:34 AM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274275767 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2274275767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.63437231
Short name T174
Test name
Test status
Simulation time 1121925417 ps
CPU time 4.83 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:40 AM UTC 24
Peak memory 211672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63437231 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.63437231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.3772588941
Short name T337
Test name
Test status
Simulation time 25970762 ps
CPU time 1.04 seconds
Started Oct 12 12:53:31 AM UTC 24
Finished Oct 12 12:53:33 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772588941 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3772588941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.545501005
Short name T393
Test name
Test status
Simulation time 3187929934 ps
CPU time 14.88 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:51 AM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545501005 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.545501005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.567270175
Short name T182
Test name
Test status
Simulation time 3869295024 ps
CPU time 50.79 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:54:27 AM UTC 24
Peak memory 221452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567270175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.567270175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.3126149574
Short name T344
Test name
Test status
Simulation time 88968949 ps
CPU time 1.35 seconds
Started Oct 12 12:53:32 AM UTC 24
Finished Oct 12 12:53:35 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126149574 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.3126149574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.2534913489
Short name T361
Test name
Test status
Simulation time 14140489 ps
CPU time 0.81 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:53:40 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534913489 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.2534913489
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.289078564
Short name T364
Test name
Test status
Simulation time 56673849 ps
CPU time 1.26 seconds
Started Oct 12 12:53:37 AM UTC 24
Finished Oct 12 12:53:40 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289078564 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.289078564
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.4277188580
Short name T353
Test name
Test status
Simulation time 13000611 ps
CPU time 1.01 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277188580 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.4277188580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.363014201
Short name T362
Test name
Test status
Simulation time 35952933 ps
CPU time 1.19 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:53:40 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363014201 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.363014201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.3633355549
Short name T354
Test name
Test status
Simulation time 93608595 ps
CPU time 1.25 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633355549 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3633355549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.4190874191
Short name T191
Test name
Test status
Simulation time 1543139994 ps
CPU time 9.65 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190874191 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.4190874191
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.413596415
Short name T368
Test name
Test status
Simulation time 742617719 ps
CPU time 5.85 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:42 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413596415 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.413596415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.572235325
Short name T357
Test name
Test status
Simulation time 139909962 ps
CPU time 1.65 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:38 AM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572235325 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.572235325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.221601788
Short name T363
Test name
Test status
Simulation time 58569502 ps
CPU time 1.38 seconds
Started Oct 12 12:53:37 AM UTC 24
Finished Oct 12 12:53:40 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221601788 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.221601788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2625893049
Short name T360
Test name
Test status
Simulation time 54491428 ps
CPU time 1.15 seconds
Started Oct 12 12:53:37 AM UTC 24
Finished Oct 12 12:53:40 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625893049
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.2625893049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.1098351518
Short name T356
Test name
Test status
Simulation time 69808118 ps
CPU time 1.39 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:38 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098351518 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1098351518
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.3307268563
Short name T367
Test name
Test status
Simulation time 198543010 ps
CPU time 1.85 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:53:41 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307268563 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3307268563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.4015399092
Short name T352
Test name
Test status
Simulation time 21139746 ps
CPU time 1.22 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015399092 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.4015399092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.2911105890
Short name T106
Test name
Test status
Simulation time 8021076851 ps
CPU time 37.52 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:54:17 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911105890 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.2911105890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.4047044733
Short name T211
Test name
Test status
Simulation time 4266379788 ps
CPU time 46.24 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 221440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047044733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.4047044733
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.1442747071
Short name T355
Test name
Test status
Simulation time 20980338 ps
CPU time 1.08 seconds
Started Oct 12 12:53:35 AM UTC 24
Finished Oct 12 12:53:37 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442747071 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1442747071
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.645077816
Short name T377
Test name
Test status
Simulation time 12506752 ps
CPU time 0.88 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645077816 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.645077816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2647826816
Short name T379
Test name
Test status
Simulation time 27809075 ps
CPU time 1.2 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647826816 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.2647826816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.3091069667
Short name T374
Test name
Test status
Simulation time 52728281 ps
CPU time 1.08 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091069667 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.3091069667
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.223550068
Short name T382
Test name
Test status
Simulation time 23435819 ps
CPU time 1.3 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223550068 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.223550068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.2489103602
Short name T365
Test name
Test status
Simulation time 21483538 ps
CPU time 1.14 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:53:40 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489103602 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2489103602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.2465202239
Short name T396
Test name
Test status
Simulation time 1641721031 ps
CPU time 13.01 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:53:52 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465202239 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2465202239
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.1001530726
Short name T384
Test name
Test status
Simulation time 531379377 ps
CPU time 2.84 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:44 AM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001530726 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.1001530726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.2248546516
Short name T375
Test name
Test status
Simulation time 36649207 ps
CPU time 1.2 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248546516 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.2248546516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.179334808
Short name T376
Test name
Test status
Simulation time 49920989 ps
CPU time 1.01 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179334808 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.179334808
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2421491839
Short name T371
Test name
Test status
Simulation time 19966857 ps
CPU time 0.84 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421491839
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.2421491839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.3107373006
Short name T370
Test name
Test status
Simulation time 52128302 ps
CPU time 0.98 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 209228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107373006 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3107373006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.3933061625
Short name T175
Test name
Test status
Simulation time 363206446 ps
CPU time 2.11 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:44 AM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933061625 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.3933061625
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.2220691095
Short name T366
Test name
Test status
Simulation time 131140059 ps
CPU time 1.32 seconds
Started Oct 12 12:53:38 AM UTC 24
Finished Oct 12 12:53:41 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220691095 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2220691095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.883459121
Short name T420
Test name
Test status
Simulation time 5112792103 ps
CPU time 20.38 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:54:03 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883459121 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.883459121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.327112999
Short name T686
Test name
Test status
Simulation time 23592436849 ps
CPU time 109.52 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:55:33 AM UTC 24
Peak memory 221776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327112999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.327112999
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.411524714
Short name T373
Test name
Test status
Simulation time 21075461 ps
CPU time 1.08 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411524714 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.411524714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.61105980
Short name T101
Test name
Test status
Simulation time 16682591 ps
CPU time 0.84 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61105980 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.61105980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.924237263
Short name T91
Test name
Test status
Simulation time 78582054 ps
CPU time 0.99 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924237263 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.924237263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.2028246691
Short name T20
Test name
Test status
Simulation time 44613335 ps
CPU time 0.76 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028246691 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2028246691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.4231583343
Short name T48
Test name
Test status
Simulation time 13165718 ps
CPU time 0.74 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231583343 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.4231583343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.1992951866
Short name T21
Test name
Test status
Simulation time 30559348 ps
CPU time 0.93 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 209796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992951866 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1992951866
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.2174016933
Short name T9
Test name
Test status
Simulation time 1278262281 ps
CPU time 10.54 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:53:03 AM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174016933 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2174016933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.584332023
Short name T35
Test name
Test status
Simulation time 2083158517 ps
CPU time 8.75 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:53:01 AM UTC 24
Peak memory 211816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584332023 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.584332023
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2419263103
Short name T165
Test name
Test status
Simulation time 23491506 ps
CPU time 0.86 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419263103
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.2419263103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.1342507950
Short name T18
Test name
Test status
Simulation time 11541526 ps
CPU time 0.72 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342507950 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1342507950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.949150628
Short name T44
Test name
Test status
Simulation time 738227056 ps
CPU time 3.06 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:56 AM UTC 24
Peak memory 211676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949150628 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.949150628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.1931321021
Short name T109
Test name
Test status
Simulation time 1073131778 ps
CPU time 5.37 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 243960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931321021 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.1931321021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.3549645715
Short name T19
Test name
Test status
Simulation time 25708530 ps
CPU time 0.82 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549645715 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3549645715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.3910369110
Short name T67
Test name
Test status
Simulation time 9219650295 ps
CPU time 37.16 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:53:30 AM UTC 24
Peak memory 212156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910369110 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.3910369110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.2905596072
Short name T469
Test name
Test status
Simulation time 19004945657 ps
CPU time 93.84 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:54:27 AM UTC 24
Peak memory 221496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905596072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2905596072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.1779963011
Short name T22
Test name
Test status
Simulation time 27123668 ps
CPU time 0.88 seconds
Started Oct 12 12:52:51 AM UTC 24
Finished Oct 12 12:52:53 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779963011 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1779963011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.4001635621
Short name T196
Test name
Test status
Simulation time 24333224 ps
CPU time 0.84 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001635621 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.4001635621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.1373928050
Short name T194
Test name
Test status
Simulation time 17787249 ps
CPU time 1.07 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373928050 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.1373928050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.1837767629
Short name T192
Test name
Test status
Simulation time 26944238 ps
CPU time 0.74 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837767629 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1837767629
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.3625735757
Short name T388
Test name
Test status
Simulation time 47025417 ps
CPU time 1.08 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625735757 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.3625735757
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.2374858157
Short name T380
Test name
Test status
Simulation time 39761165 ps
CPU time 0.94 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374858157 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.2374858157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.1738238984
Short name T350
Test name
Test status
Simulation time 1056680155 ps
CPU time 5.09 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:50 AM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738238984 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1738238984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.2832028809
Short name T404
Test name
Test status
Simulation time 2177110650 ps
CPU time 16.07 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832028809 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.2832028809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.3566013535
Short name T193
Test name
Test status
Simulation time 20010302 ps
CPU time 0.79 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566013535 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.3566013535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3270959574
Short name T197
Test name
Test status
Simulation time 28961351 ps
CPU time 1.17 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270959574
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.3270959574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3928616001
Short name T195
Test name
Test status
Simulation time 108983372 ps
CPU time 1.27 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928616001
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.3928616001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.3578589208
Short name T189
Test name
Test status
Simulation time 16200018 ps
CPU time 0.83 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578589208 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3578589208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.2996724999
Short name T349
Test name
Test status
Simulation time 188021987 ps
CPU time 1.63 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:47 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996724999 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.2996724999
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.2282841210
Short name T381
Test name
Test status
Simulation time 19449671 ps
CPU time 1.07 seconds
Started Oct 12 12:53:41 AM UTC 24
Finished Oct 12 12:53:43 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282841210 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.2282841210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.2295189759
Short name T554
Test name
Test status
Simulation time 9132990996 ps
CPU time 69.19 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:54:55 AM UTC 24
Peak memory 212040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295189759 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.2295189759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.791224979
Short name T210
Test name
Test status
Simulation time 5782244047 ps
CPU time 30.72 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 221512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791224979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.791224979
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.4075676663
Short name T190
Test name
Test status
Simulation time 39444075 ps
CPU time 0.83 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075676663 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.4075676663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.806853400
Short name T398
Test name
Test status
Simulation time 17713696 ps
CPU time 0.84 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:53:57 AM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806853400 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.806853400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.1548021483
Short name T97
Test name
Test status
Simulation time 30586984 ps
CPU time 0.97 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:53:51 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548021483 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.1548021483
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.1832987302
Short name T392
Test name
Test status
Simulation time 143869761 ps
CPU time 1.19 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:53:51 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832987302 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1832987302
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.1426735145
Short name T394
Test name
Test status
Simulation time 51947284 ps
CPU time 0.98 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:53:51 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426735145 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.1426735145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.2628248925
Short name T389
Test name
Test status
Simulation time 29758377 ps
CPU time 1.05 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:47 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628248925 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2628248925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.3502865395
Short name T432
Test name
Test status
Simulation time 3297013262 ps
CPU time 11.12 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:54:07 AM UTC 24
Peak memory 212120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502865395 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3502865395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.268336899
Short name T410
Test name
Test status
Simulation time 986043954 ps
CPU time 5.94 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268336899 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.268336899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.3494305485
Short name T390
Test name
Test status
Simulation time 26734431 ps
CPU time 1.02 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:53:50 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494305485 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3494305485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.57081171
Short name T395
Test name
Test status
Simulation time 240276775 ps
CPU time 1.67 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:53:51 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57081171 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.57081171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3392474637
Short name T391
Test name
Test status
Simulation time 31776072 ps
CPU time 0.92 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:53:50 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392474637
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.3392474637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.2549542292
Short name T372
Test name
Test status
Simulation time 72537010 ps
CPU time 1 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:53:50 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549542292 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2549542292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.2138800523
Short name T176
Test name
Test status
Simulation time 907277796 ps
CPU time 5.06 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:53:55 AM UTC 24
Peak memory 211724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138800523 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.2138800523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.2172238005
Short name T387
Test name
Test status
Simulation time 49915190 ps
CPU time 0.93 seconds
Started Oct 12 12:53:44 AM UTC 24
Finished Oct 12 12:53:46 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172238005 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.2172238005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.4153778387
Short name T489
Test name
Test status
Simulation time 5057024753 ps
CPU time 37.32 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153778387 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.4153778387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.575537375
Short name T183
Test name
Test status
Simulation time 4161130606 ps
CPU time 56.88 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:54:47 AM UTC 24
Peak memory 221456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575537375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.575537375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.4264175572
Short name T397
Test name
Test status
Simulation time 24007863 ps
CPU time 0.92 seconds
Started Oct 12 12:53:47 AM UTC 24
Finished Oct 12 12:53:56 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264175572 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.4264175572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.142125272
Short name T400
Test name
Test status
Simulation time 13255734 ps
CPU time 0.92 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142125272 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.142125272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.4121819998
Short name T419
Test name
Test status
Simulation time 73649796 ps
CPU time 0.89 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:03 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121819998 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.4121819998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.642936890
Short name T409
Test name
Test status
Simulation time 29727787 ps
CPU time 1.02 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642936890 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.642936890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.2999724508
Short name T421
Test name
Test status
Simulation time 88814600 ps
CPU time 1.05 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:03 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999724508 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.2999724508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.2462611929
Short name T406
Test name
Test status
Simulation time 41131647 ps
CPU time 1.17 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462611929 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2462611929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.735136879
Short name T437
Test name
Test status
Simulation time 2135627267 ps
CPU time 10.41 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:54:11 AM UTC 24
Peak memory 212044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735136879 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.735136879
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.416307444
Short name T399
Test name
Test status
Simulation time 1340903373 ps
CPU time 7.1 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:53:57 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416307444 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.416307444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.3739481373
Short name T414
Test name
Test status
Simulation time 63084341 ps
CPU time 1.17 seconds
Started Oct 12 12:53:56 AM UTC 24
Finished Oct 12 12:54:02 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739481373 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.3739481373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2077317394
Short name T422
Test name
Test status
Simulation time 147905113 ps
CPU time 1.21 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:03 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077317394
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.2077317394
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1844300736
Short name T407
Test name
Test status
Simulation time 28815610 ps
CPU time 0.9 seconds
Started Oct 12 12:53:56 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844300736
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.1844300736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.2883711068
Short name T412
Test name
Test status
Simulation time 76723407 ps
CPU time 1.21 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883711068 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.2883711068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.457462448
Short name T424
Test name
Test status
Simulation time 764606893 ps
CPU time 4.68 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:05 AM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457462448 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.457462448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.1995057758
Short name T161
Test name
Test status
Simulation time 24115118 ps
CPU time 1.01 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:53:51 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995057758 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1995057758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.2311302923
Short name T448
Test name
Test status
Simulation time 1528676768 ps
CPU time 12.95 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:13 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311302923 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2311302923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.1106429766
Short name T64
Test name
Test status
Simulation time 843124534 ps
CPU time 7.38 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:07 AM UTC 24
Peak memory 227800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106429766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1106429766
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.1953486161
Short name T411
Test name
Test status
Simulation time 50010272 ps
CPU time 1.1 seconds
Started Oct 12 12:53:48 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953486161 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1953486161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.1836795025
Short name T451
Test name
Test status
Simulation time 43926036 ps
CPU time 0.82 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836795025 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.1836795025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1398611147
Short name T425
Test name
Test status
Simulation time 27635615 ps
CPU time 0.95 seconds
Started Oct 12 12:54:03 AM UTC 24
Finished Oct 12 12:54:05 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398611147 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.1398611147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.1816253207
Short name T408
Test name
Test status
Simulation time 45302244 ps
CPU time 0.79 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816253207 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1816253207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.3099636877
Short name T413
Test name
Test status
Simulation time 28058396 ps
CPU time 1.26 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099636877 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3099636877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.1740303088
Short name T436
Test name
Test status
Simulation time 2230015770 ps
CPU time 10.28 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:10 AM UTC 24
Peak memory 211864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740303088 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1740303088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.289962605
Short name T433
Test name
Test status
Simulation time 1339490380 ps
CPU time 8.51 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:09 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289962605 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.289962605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.3298217772
Short name T417
Test name
Test status
Simulation time 83097295 ps
CPU time 1.3 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:02 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298217772 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.3298217772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1781359422
Short name T418
Test name
Test status
Simulation time 63738564 ps
CPU time 1.07 seconds
Started Oct 12 12:54:00 AM UTC 24
Finished Oct 12 12:54:03 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781359422
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.1781359422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1737013592
Short name T416
Test name
Test status
Simulation time 68498238 ps
CPU time 1.19 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:02 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737013592
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.1737013592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.1518497729
Short name T403
Test name
Test status
Simulation time 16269865 ps
CPU time 0.76 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518497729 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1518497729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.1935827718
Short name T401
Test name
Test status
Simulation time 1324038192 ps
CPU time 4.71 seconds
Started Oct 12 12:54:03 AM UTC 24
Finished Oct 12 12:54:19 AM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935827718 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1935827718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.493156707
Short name T402
Test name
Test status
Simulation time 28598621 ps
CPU time 0.95 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493156707 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.493156707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.4034398019
Short name T471
Test name
Test status
Simulation time 3457249409 ps
CPU time 15 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:30 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034398019 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.4034398019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.4276550572
Short name T629
Test name
Test status
Simulation time 3824983061 ps
CPU time 66.06 seconds
Started Oct 12 12:54:03 AM UTC 24
Finished Oct 12 12:55:21 AM UTC 24
Peak memory 221500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276550572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.4276550572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.1621796522
Short name T405
Test name
Test status
Simulation time 12770249 ps
CPU time 0.74 seconds
Started Oct 12 12:53:58 AM UTC 24
Finished Oct 12 12:54:01 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621796522 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.1621796522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.4214364011
Short name T498
Test name
Test status
Simulation time 21069565 ps
CPU time 0.89 seconds
Started Oct 12 12:54:05 AM UTC 24
Finished Oct 12 12:54:35 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214364011 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.4214364011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3351135035
Short name T430
Test name
Test status
Simulation time 25149947 ps
CPU time 1.02 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:06 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351135035 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.3351135035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.1287913284
Short name T450
Test name
Test status
Simulation time 12041579 ps
CPU time 0.71 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287913284 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.1287913284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.1800865482
Short name T428
Test name
Test status
Simulation time 42486782 ps
CPU time 0.9 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:06 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800865482 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1800865482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.3184108661
Short name T496
Test name
Test status
Simulation time 19010891 ps
CPU time 1.03 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184108661 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3184108661
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.1951304972
Short name T519
Test name
Test status
Simulation time 1408813550 ps
CPU time 8.82 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:42 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951304972 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1951304972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.4000480065
Short name T502
Test name
Test status
Simulation time 421633530 ps
CPU time 2.33 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:35 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000480065 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.4000480065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.858294522
Short name T431
Test name
Test status
Simulation time 102239627 ps
CPU time 1.36 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:06 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858294522 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.858294522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1382688960
Short name T429
Test name
Test status
Simulation time 41761515 ps
CPU time 0.96 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:06 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382688960
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.1382688960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.605171108
Short name T427
Test name
Test status
Simulation time 23558396 ps
CPU time 0.94 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:06 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605171108 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.605171108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.381523747
Short name T426
Test name
Test status
Simulation time 16570765 ps
CPU time 0.94 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:06 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381523747 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.381523747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.2651753352
Short name T435
Test name
Test status
Simulation time 1177673621 ps
CPU time 4.12 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:09 AM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651753352 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.2651753352
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.1175386216
Short name T452
Test name
Test status
Simulation time 23076826 ps
CPU time 0.92 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175386216 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.1175386216
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.309834150
Short name T577
Test name
Test status
Simulation time 4911387503 ps
CPU time 26.31 seconds
Started Oct 12 12:54:05 AM UTC 24
Finished Oct 12 12:55:00 AM UTC 24
Peak memory 211896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309834150 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.309834150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.1089183901
Short name T582
Test name
Test status
Simulation time 3392046271 ps
CPU time 47.99 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:55:04 AM UTC 24
Peak memory 221500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089183901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.1089183901
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.2084273045
Short name T493
Test name
Test status
Simulation time 21705597 ps
CPU time 0.81 seconds
Started Oct 12 12:54:04 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084273045 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2084273045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.3946738267
Short name T449
Test name
Test status
Simulation time 16936735 ps
CPU time 0.74 seconds
Started Oct 12 12:54:10 AM UTC 24
Finished Oct 12 12:54:15 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946738267 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.3946738267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.4023314254
Short name T443
Test name
Test status
Simulation time 24449146 ps
CPU time 0.9 seconds
Started Oct 12 12:54:07 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023314254 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.4023314254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.2441149327
Short name T442
Test name
Test status
Simulation time 72921588 ps
CPU time 0.89 seconds
Started Oct 12 12:54:07 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441149327 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.2441149327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.2372088350
Short name T438
Test name
Test status
Simulation time 21828428 ps
CPU time 0.81 seconds
Started Oct 12 12:54:08 AM UTC 24
Finished Oct 12 12:54:11 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372088350 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.2372088350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.3897652047
Short name T499
Test name
Test status
Simulation time 34290319 ps
CPU time 0.9 seconds
Started Oct 12 12:54:05 AM UTC 24
Finished Oct 12 12:54:35 AM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897652047 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3897652047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.2864018104
Short name T518
Test name
Test status
Simulation time 797498230 ps
CPU time 6.8 seconds
Started Oct 12 12:54:05 AM UTC 24
Finished Oct 12 12:54:41 AM UTC 24
Peak memory 211788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864018104 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2864018104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.1244623677
Short name T520
Test name
Test status
Simulation time 1338078673 ps
CPU time 9.81 seconds
Started Oct 12 12:54:06 AM UTC 24
Finished Oct 12 12:54:44 AM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244623677 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.1244623677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.4163207473
Short name T446
Test name
Test status
Simulation time 95567100 ps
CPU time 1.15 seconds
Started Oct 12 12:54:07 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163207473 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.4163207473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2198943192
Short name T444
Test name
Test status
Simulation time 31358827 ps
CPU time 0.86 seconds
Started Oct 12 12:54:07 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198943192
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.2198943192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.1897302439
Short name T445
Test name
Test status
Simulation time 85195207 ps
CPU time 1.05 seconds
Started Oct 12 12:54:07 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897302439
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.1897302439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.2875125756
Short name T440
Test name
Test status
Simulation time 18859503 ps
CPU time 0.79 seconds
Started Oct 12 12:54:07 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875125756 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2875125756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.3214011444
Short name T439
Test name
Test status
Simulation time 149877777 ps
CPU time 1.43 seconds
Started Oct 12 12:54:08 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214011444 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3214011444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.22602473
Short name T500
Test name
Test status
Simulation time 82060960 ps
CPU time 1.03 seconds
Started Oct 12 12:54:05 AM UTC 24
Finished Oct 12 12:54:35 AM UTC 24
Peak memory 210232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22602473 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.22602473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.1712469181
Short name T506
Test name
Test status
Simulation time 3152222512 ps
CPU time 24.43 seconds
Started Oct 12 12:54:10 AM UTC 24
Finished Oct 12 12:54:36 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712469181 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.1712469181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.2903538249
Short name T556
Test name
Test status
Simulation time 2749682490 ps
CPU time 45.2 seconds
Started Oct 12 12:54:09 AM UTC 24
Finished Oct 12 12:54:56 AM UTC 24
Peak memory 221496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903538249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.2903538249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.4119278922
Short name T441
Test name
Test status
Simulation time 58432607 ps
CPU time 0.87 seconds
Started Oct 12 12:54:07 AM UTC 24
Finished Oct 12 12:54:12 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119278922 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.4119278922
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.242920099
Short name T478
Test name
Test status
Simulation time 55829797 ps
CPU time 0.84 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 208976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242920099 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.242920099
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.1891803894
Short name T467
Test name
Test status
Simulation time 29178652 ps
CPU time 0.84 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891803894 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.1891803894
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.504504511
Short name T456
Test name
Test status
Simulation time 50811525 ps
CPU time 0.82 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504504511 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.504504511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.89053839
Short name T464
Test name
Test status
Simulation time 19219842 ps
CPU time 0.71 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89053839 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.89053839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.2130333998
Short name T494
Test name
Test status
Simulation time 25381922 ps
CPU time 0.95 seconds
Started Oct 12 12:54:12 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130333998 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.2130333998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.1665854634
Short name T516
Test name
Test status
Simulation time 924071142 ps
CPU time 5.98 seconds
Started Oct 12 12:54:12 AM UTC 24
Finished Oct 12 12:54:39 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665854634 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.1665854634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.3240213210
Short name T514
Test name
Test status
Simulation time 500824728 ps
CPU time 4.3 seconds
Started Oct 12 12:54:12 AM UTC 24
Finished Oct 12 12:54:37 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240213210 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.3240213210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.4261824015
Short name T455
Test name
Test status
Simulation time 27730057 ps
CPU time 0.85 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261824015 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.4261824015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.2554081146
Short name T468
Test name
Test status
Simulation time 65649955 ps
CPU time 0.85 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554081146
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.2554081146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1542447956
Short name T466
Test name
Test status
Simulation time 47682349 ps
CPU time 0.88 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542447956
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.1542447956
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.2812968504
Short name T492
Test name
Test status
Simulation time 27248306 ps
CPU time 0.73 seconds
Started Oct 12 12:54:12 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 209228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812968504 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2812968504
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.601263225
Short name T470
Test name
Test status
Simulation time 662952894 ps
CPU time 3.64 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:29 AM UTC 24
Peak memory 211792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601263225 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.601263225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.3475664912
Short name T495
Test name
Test status
Simulation time 15953774 ps
CPU time 0.89 seconds
Started Oct 12 12:54:12 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475664912 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3475664912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.3892198184
Short name T107
Test name
Test status
Simulation time 9106278779 ps
CPU time 47.15 seconds
Started Oct 12 12:54:14 AM UTC 24
Finished Oct 12 12:55:20 AM UTC 24
Peak memory 211892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892198184 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.3892198184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.499885721
Short name T663
Test name
Test status
Simulation time 5135851078 ps
CPU time 54.71 seconds
Started Oct 12 12:54:14 AM UTC 24
Finished Oct 12 12:55:28 AM UTC 24
Peak memory 221824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499885721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.499885721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.489149777
Short name T454
Test name
Test status
Simulation time 21593725 ps
CPU time 0.84 seconds
Started Oct 12 12:54:13 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489149777 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.489149777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.3995641724
Short name T485
Test name
Test status
Simulation time 176807765 ps
CPU time 1.2 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995641724 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.3995641724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3855860770
Short name T487
Test name
Test status
Simulation time 218464645 ps
CPU time 1.34 seconds
Started Oct 12 12:54:20 AM UTC 24
Finished Oct 12 12:54:33 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855860770 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.3855860770
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.1397234306
Short name T463
Test name
Test status
Simulation time 23994149 ps
CPU time 0.65 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397234306 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1397234306
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.1785363403
Short name T491
Test name
Test status
Simulation time 65616872 ps
CPU time 0.89 seconds
Started Oct 12 12:54:21 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785363403 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.1785363403
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.3407622295
Short name T479
Test name
Test status
Simulation time 30442851 ps
CPU time 0.92 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407622295 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3407622295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.3348404439
Short name T515
Test name
Test status
Simulation time 1286500129 ps
CPU time 7.66 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:39 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348404439 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.3348404439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.2194854003
Short name T501
Test name
Test status
Simulation time 497697857 ps
CPU time 4.16 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:35 AM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194854003 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.2194854003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.245199097
Short name T459
Test name
Test status
Simulation time 54796530 ps
CPU time 0.8 seconds
Started Oct 12 12:54:18 AM UTC 24
Finished Oct 12 12:54:21 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245199097 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.245199097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.154230500
Short name T460
Test name
Test status
Simulation time 52714334 ps
CPU time 0.8 seconds
Started Oct 12 12:54:19 AM UTC 24
Finished Oct 12 12:54:21 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154230500 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.154230500
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1464984362
Short name T461
Test name
Test status
Simulation time 175066205 ps
CPU time 1.17 seconds
Started Oct 12 12:54:18 AM UTC 24
Finished Oct 12 12:54:21 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464984362
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.1464984362
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.533994368
Short name T475
Test name
Test status
Simulation time 15398492 ps
CPU time 0.73 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533994368 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.533994368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.1493155938
Short name T497
Test name
Test status
Simulation time 353475288 ps
CPU time 1.63 seconds
Started Oct 12 12:54:21 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493155938 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1493155938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.77022179
Short name T477
Test name
Test status
Simulation time 23067023 ps
CPU time 0.8 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77022179 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.77022179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.494191035
Short name T523
Test name
Test status
Simulation time 3541602462 ps
CPU time 15.01 seconds
Started Oct 12 12:54:26 AM UTC 24
Finished Oct 12 12:54:49 AM UTC 24
Peak memory 211864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494191035 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.494191035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.2611325893
Short name T185
Test name
Test status
Simulation time 7414837000 ps
CPU time 29.99 seconds
Started Oct 12 12:54:22 AM UTC 24
Finished Oct 12 12:55:01 AM UTC 24
Peak memory 221496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611325893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2611325893
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.461572507
Short name T458
Test name
Test status
Simulation time 15963929 ps
CPU time 0.69 seconds
Started Oct 12 12:54:17 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461572507 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.461572507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.2511805278
Short name T503
Test name
Test status
Simulation time 22053697 ps
CPU time 0.89 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:36 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511805278 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.2511805278
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.846875061
Short name T486
Test name
Test status
Simulation time 32477648 ps
CPU time 0.84 seconds
Started Oct 12 12:54:30 AM UTC 24
Finished Oct 12 12:54:33 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846875061 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.846875061
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.1911716814
Short name T484
Test name
Test status
Simulation time 49535201 ps
CPU time 0.78 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911716814 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1911716814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.1902281294
Short name T490
Test name
Test status
Simulation time 17970105 ps
CPU time 0.77 seconds
Started Oct 12 12:54:32 AM UTC 24
Finished Oct 12 12:54:34 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902281294 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.1902281294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.1192124667
Short name T480
Test name
Test status
Simulation time 54159078 ps
CPU time 0.85 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192124667 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1192124667
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.4022349796
Short name T521
Test name
Test status
Simulation time 2366113063 ps
CPU time 12.4 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:44 AM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022349796 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.4022349796
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.319975336
Short name T488
Test name
Test status
Simulation time 307172045 ps
CPU time 1.86 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:33 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319975336 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.319975336
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.1341107685
Short name T474
Test name
Test status
Simulation time 24703232 ps
CPU time 0.81 seconds
Started Oct 12 12:54:28 AM UTC 24
Finished Oct 12 12:54:31 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341107685 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.1341107685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2414532557
Short name T473
Test name
Test status
Simulation time 46935496 ps
CPU time 0.78 seconds
Started Oct 12 12:54:29 AM UTC 24
Finished Oct 12 12:54:31 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414532557
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.2414532557
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1762335541
Short name T472
Test name
Test status
Simulation time 25101822 ps
CPU time 0.77 seconds
Started Oct 12 12:54:28 AM UTC 24
Finished Oct 12 12:54:31 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762335541
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.1762335541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.2958381518
Short name T481
Test name
Test status
Simulation time 26053129 ps
CPU time 0.81 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958381518 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2958381518
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.1714713301
Short name T517
Test name
Test status
Simulation time 1008862681 ps
CPU time 5.62 seconds
Started Oct 12 12:54:33 AM UTC 24
Finished Oct 12 12:54:40 AM UTC 24
Peak memory 211724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714713301 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1714713301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.2312864215
Short name T483
Test name
Test status
Simulation time 108887014 ps
CPU time 1.08 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312864215 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.2312864215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.4263898583
Short name T522
Test name
Test status
Simulation time 1847561039 ps
CPU time 9.86 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:45 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263898583 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.4263898583
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.1288781600
Short name T186
Test name
Test status
Simulation time 5339178148 ps
CPU time 32.64 seconds
Started Oct 12 12:54:33 AM UTC 24
Finished Oct 12 12:55:08 AM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288781600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.1288781600
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.1129139810
Short name T482
Test name
Test status
Simulation time 25793338 ps
CPU time 0.83 seconds
Started Oct 12 12:54:27 AM UTC 24
Finished Oct 12 12:54:32 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129139810 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1129139810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.829236998
Short name T528
Test name
Test status
Simulation time 25852107 ps
CPU time 1.01 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829236998 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.829236998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.585198891
Short name T527
Test name
Test status
Simulation time 28429207 ps
CPU time 1 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585198891 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.585198891
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.2897163256
Short name T509
Test name
Test status
Simulation time 40610994 ps
CPU time 0.89 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:37 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897163256 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2897163256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.1905376232
Short name T524
Test name
Test status
Simulation time 16541301 ps
CPU time 0.81 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905376232 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.1905376232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.2289173348
Short name T507
Test name
Test status
Simulation time 33853676 ps
CPU time 0.78 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:36 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289173348 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.2289173348
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.518386805
Short name T549
Test name
Test status
Simulation time 2237882133 ps
CPU time 17.04 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:53 AM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518386805 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.518386805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.220869040
Short name T513
Test name
Test status
Simulation time 142701904 ps
CPU time 1.72 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:37 AM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220869040 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.220869040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.1519626114
Short name T512
Test name
Test status
Simulation time 35534327 ps
CPU time 0.93 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:37 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519626114 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.1519626114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.3048042788
Short name T505
Test name
Test status
Simulation time 50644154 ps
CPU time 0.92 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:36 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048042788
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.3048042788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2390043929
Short name T504
Test name
Test status
Simulation time 17806839 ps
CPU time 0.77 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:36 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390043929
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.2390043929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.998279424
Short name T510
Test name
Test status
Simulation time 43884957 ps
CPU time 0.92 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:37 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998279424 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.998279424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.516244423
Short name T547
Test name
Test status
Simulation time 526140665 ps
CPU time 2.69 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:53 AM UTC 24
Peak memory 211456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516244423 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.516244423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.1276011133
Short name T508
Test name
Test status
Simulation time 40008383 ps
CPU time 0.89 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:37 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276011133 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1276011133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.163532710
Short name T753
Test name
Test status
Simulation time 8846436235 ps
CPU time 68.57 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:55:59 AM UTC 24
Peak memory 211868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163532710 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.163532710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.3277904130
Short name T755
Test name
Test status
Simulation time 5032546580 ps
CPU time 69.6 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:56:00 AM UTC 24
Peak memory 228400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277904130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.3277904130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.3668657393
Short name T511
Test name
Test status
Simulation time 28516160 ps
CPU time 0.93 seconds
Started Oct 12 12:54:34 AM UTC 24
Finished Oct 12 12:54:37 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668657393 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3668657393
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.1285617020
Short name T215
Test name
Test status
Simulation time 16090600 ps
CPU time 0.77 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285617020 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.1285617020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.270305019
Short name T166
Test name
Test status
Simulation time 18415816 ps
CPU time 0.78 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270305019 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.270305019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.1726183911
Short name T198
Test name
Test status
Simulation time 174050452 ps
CPU time 1.07 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726183911 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.1726183911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.961572642
Short name T209
Test name
Test status
Simulation time 17298106 ps
CPU time 0.71 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961572642 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.961572642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.1277948645
Short name T167
Test name
Test status
Simulation time 72297838 ps
CPU time 1.05 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277948645 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1277948645
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.714000086
Short name T31
Test name
Test status
Simulation time 1729673069 ps
CPU time 7.99 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:53:01 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714000086 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.714000086
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.4021608530
Short name T53
Test name
Test status
Simulation time 2213438817 ps
CPU time 7.12 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:53:00 AM UTC 24
Peak memory 211892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021608530 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.4021608530
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.1349880305
Short name T212
Test name
Test status
Simulation time 42493821 ps
CPU time 0.89 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349880305 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1349880305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.674761025
Short name T216
Test name
Test status
Simulation time 39069376 ps
CPU time 0.88 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674761025 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.674761025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.952301128
Short name T204
Test name
Test status
Simulation time 98084330 ps
CPU time 1.08 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952301128 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.952301128
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.2689943855
Short name T51
Test name
Test status
Simulation time 866501945 ps
CPU time 5.27 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689943855 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.2689943855
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.2980703540
Short name T99
Test name
Test status
Simulation time 413306300 ps
CPU time 3.01 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:56 AM UTC 24
Peak memory 244216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980703540 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.2980703540
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.2830828801
Short name T137
Test name
Test status
Simulation time 69320774 ps
CPU time 1.02 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830828801 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2830828801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.3082278186
Short name T453
Test name
Test status
Simulation time 14336179522 ps
CPU time 81.78 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:54:16 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082278186 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.3082278186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.485126506
Short name T462
Test name
Test status
Simulation time 8941145613 ps
CPU time 90.23 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:54:24 AM UTC 24
Peak memory 221476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485126506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.485126506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.184550456
Short name T217
Test name
Test status
Simulation time 51771067 ps
CPU time 1.07 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184550456 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.184550456
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.1642957994
Short name T537
Test name
Test status
Simulation time 29534914 ps
CPU time 1.09 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 209144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642957994 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.1642957994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.4126704050
Short name T533
Test name
Test status
Simulation time 152642387 ps
CPU time 1.17 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126704050 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.4126704050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.2862593259
Short name T531
Test name
Test status
Simulation time 34773060 ps
CPU time 0.8 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862593259 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2862593259
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.3128940102
Short name T535
Test name
Test status
Simulation time 31016677 ps
CPU time 1.16 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128940102 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.3128940102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.3385710090
Short name T530
Test name
Test status
Simulation time 26187254 ps
CPU time 0.96 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 210948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385710090 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.3385710090
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.3121222124
Short name T555
Test name
Test status
Simulation time 1365416836 ps
CPU time 5.2 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:55 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121222124 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3121222124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.3528562815
Short name T552
Test name
Test status
Simulation time 886035695 ps
CPU time 4.09 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:54 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528562815 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.3528562815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.3804950722
Short name T536
Test name
Test status
Simulation time 30006686 ps
CPU time 0.97 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804950722 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.3804950722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.2956698599
Short name T525
Test name
Test status
Simulation time 35210758 ps
CPU time 0.75 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956698599
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.2956698599
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3162487556
Short name T532
Test name
Test status
Simulation time 21720815 ps
CPU time 1.06 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162487556
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.3162487556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.3427955563
Short name T529
Test name
Test status
Simulation time 14431718 ps
CPU time 0.74 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427955563 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3427955563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.3718489908
Short name T544
Test name
Test status
Simulation time 342136375 ps
CPU time 2.06 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:52 AM UTC 24
Peak memory 211076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718489908 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3718489908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.357461817
Short name T540
Test name
Test status
Simulation time 160394072 ps
CPU time 1.53 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:52 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357461817 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.357461817
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.3578565433
Short name T687
Test name
Test status
Simulation time 6078899251 ps
CPU time 45.08 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:55:36 AM UTC 24
Peak memory 211512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578565433 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.3578565433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.3938711608
Short name T837
Test name
Test status
Simulation time 17894371508 ps
CPU time 103.35 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:56:35 AM UTC 24
Peak memory 228596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938711608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.3938711608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.4062090050
Short name T476
Test name
Test status
Simulation time 53748950 ps
CPU time 0.89 seconds
Started Oct 12 12:54:36 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062090050 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.4062090050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_alert_test.2829934160
Short name T542
Test name
Test status
Simulation time 29753948 ps
CPU time 0.83 seconds
Started Oct 12 12:54:50 AM UTC 24
Finished Oct 12 12:54:52 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829934160 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_alert_test.2829934160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2265447548
Short name T550
Test name
Test status
Simulation time 26836537 ps
CPU time 0.81 seconds
Started Oct 12 12:54:43 AM UTC 24
Finished Oct 12 12:54:53 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265447548 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.2265447548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.2592116881
Short name T541
Test name
Test status
Simulation time 19982309 ps
CPU time 0.96 seconds
Started Oct 12 12:54:40 AM UTC 24
Finished Oct 12 12:54:52 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592116881 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2592116881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.285304541
Short name T551
Test name
Test status
Simulation time 75077632 ps
CPU time 0.98 seconds
Started Oct 12 12:54:44 AM UTC 24
Finished Oct 12 12:54:53 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285304541 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.285304541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.1030404243
Short name T538
Test name
Test status
Simulation time 60718379 ps
CPU time 1.01 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:52 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030404243 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.1030404243
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.1612732668
Short name T584
Test name
Test status
Simulation time 1996786908 ps
CPU time 14.33 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:55:05 AM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612732668 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1612732668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.3275496222
Short name T580
Test name
Test status
Simulation time 1580122228 ps
CPU time 11.34 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:55:02 AM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275496222 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.3275496222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.1287424056
Short name T546
Test name
Test status
Simulation time 26057765 ps
CPU time 0.78 seconds
Started Oct 12 12:54:41 AM UTC 24
Finished Oct 12 12:54:53 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287424056 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.1287424056
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.4200476748
Short name T526
Test name
Test status
Simulation time 26448522 ps
CPU time 0.87 seconds
Started Oct 12 12:54:42 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200476748
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.4200476748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1739808368
Short name T545
Test name
Test status
Simulation time 21591033 ps
CPU time 0.77 seconds
Started Oct 12 12:54:41 AM UTC 24
Finished Oct 12 12:54:53 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739808368
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.1739808368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.849542897
Short name T539
Test name
Test status
Simulation time 42604533 ps
CPU time 0.92 seconds
Started Oct 12 12:54:40 AM UTC 24
Finished Oct 12 12:54:52 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849542897 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.849542897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.2546164605
Short name T553
Test name
Test status
Simulation time 562904452 ps
CPU time 2.15 seconds
Started Oct 12 12:54:44 AM UTC 24
Finished Oct 12 12:54:55 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546164605 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.2546164605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.4277078831
Short name T534
Test name
Test status
Simulation time 16885090 ps
CPU time 0.94 seconds
Started Oct 12 12:54:38 AM UTC 24
Finished Oct 12 12:54:51 AM UTC 24
Peak memory 211052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277078831 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.4277078831
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.2994009535
Short name T780
Test name
Test status
Simulation time 11333267780 ps
CPU time 79.44 seconds
Started Oct 12 12:54:49 AM UTC 24
Finished Oct 12 12:56:11 AM UTC 24
Peak memory 211788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994009535 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.2994009535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.531833023
Short name T751
Test name
Test status
Simulation time 12122572528 ps
CPU time 64.8 seconds
Started Oct 12 12:54:45 AM UTC 24
Finished Oct 12 12:55:59 AM UTC 24
Peak memory 225552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531833023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.531833023
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.3167468849
Short name T543
Test name
Test status
Simulation time 57545591 ps
CPU time 1.05 seconds
Started Oct 12 12:54:40 AM UTC 24
Finished Oct 12 12:54:52 AM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167468849 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3167468849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.602719179
Short name T564
Test name
Test status
Simulation time 27482804 ps
CPU time 0.98 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602719179 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.602719179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3444070242
Short name T563
Test name
Test status
Simulation time 47861208 ps
CPU time 1.02 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444070242 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.3444070242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.3068146
Short name T559
Test name
Test status
Simulation time 42436895 ps
CPU time 0.76 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:58 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068146 -assert nopostproc +UVM_TESTNAME=clkmg
r_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3068146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.531920709
Short name T561
Test name
Test status
Simulation time 19542211 ps
CPU time 0.91 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531920709 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.531920709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_extclk.1446479834
Short name T558
Test name
Test status
Simulation time 24478120 ps
CPU time 0.83 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:58 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446479834 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1446479834
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency.946304403
Short name T606
Test name
Test status
Simulation time 2129704402 ps
CPU time 11.86 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:10 AM UTC 24
Peak memory 211736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946304403 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.946304403
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.533783558
Short name T579
Test name
Test status
Simulation time 800679807 ps
CPU time 4.13 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:02 AM UTC 24
Peak memory 211816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533783558 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.533783558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.473052134
Short name T576
Test name
Test status
Simulation time 309887268 ps
CPU time 1.95 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:00 AM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473052134 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.473052134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1793869562
Short name T565
Test name
Test status
Simulation time 161822121 ps
CPU time 1.25 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793869562
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.1793869562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3566747629
Short name T560
Test name
Test status
Simulation time 12921292 ps
CPU time 0.72 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566747629
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.3566747629
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.157131596
Short name T557
Test name
Test status
Simulation time 15662180 ps
CPU time 0.79 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:58 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157131596 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.157131596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.2852596202
Short name T578
Test name
Test status
Simulation time 570734239 ps
CPU time 3.1 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:01 AM UTC 24
Peak memory 211900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852596202 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.2852596202
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_smoke.3274686065
Short name T548
Test name
Test status
Simulation time 30362485 ps
CPU time 0.92 seconds
Started Oct 12 12:54:51 AM UTC 24
Finished Oct 12 12:54:53 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274686065 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3274686065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.725504575
Short name T656
Test name
Test status
Simulation time 3386293798 ps
CPU time 26.15 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725504575 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.725504575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.3174343722
Short name T661
Test name
Test status
Simulation time 3117186426 ps
CPU time 28.93 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:27 AM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174343722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3174343722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.3151861606
Short name T566
Test name
Test status
Simulation time 98505135 ps
CPU time 1.37 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151861606 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3151861606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.3706141734
Short name T592
Test name
Test status
Simulation time 160849796 ps
CPU time 1.34 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706141734 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.3706141734
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.1790411467
Short name T573
Test name
Test status
Simulation time 64389805 ps
CPU time 0.92 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:00 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790411467 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.1790411467
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.1117356398
Short name T569
Test name
Test status
Simulation time 15085421 ps
CPU time 0.91 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 208464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117356398 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1117356398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.1793788764
Short name T575
Test name
Test status
Simulation time 89329746 ps
CPU time 1.12 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:00 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793788764 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.1793788764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.3870768990
Short name T567
Test name
Test status
Simulation time 37064082 ps
CPU time 0.97 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870768990 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.3870768990
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.3772663676
Short name T583
Test name
Test status
Simulation time 924155349 ps
CPU time 5.55 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:04 AM UTC 24
Peak memory 211848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772663676 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3772663676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.1437426144
Short name T603
Test name
Test status
Simulation time 2430914222 ps
CPU time 9.45 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:08 AM UTC 24
Peak memory 212140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437426144 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.1437426144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.3647783478
Short name T570
Test name
Test status
Simulation time 15157258 ps
CPU time 0.86 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647783478 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.3647783478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1297125868
Short name T571
Test name
Test status
Simulation time 18072760 ps
CPU time 0.78 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:00 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297125868
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.1297125868
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3394561366
Short name T574
Test name
Test status
Simulation time 142100735 ps
CPU time 1.16 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:00 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394561366
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.3394561366
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.1826279447
Short name T568
Test name
Test status
Simulation time 26191493 ps
CPU time 0.91 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826279447 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1826279447
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.3485645357
Short name T581
Test name
Test status
Simulation time 500652013 ps
CPU time 3.14 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:02 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485645357 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.3485645357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.2023855878
Short name T562
Test name
Test status
Simulation time 23462420 ps
CPU time 0.83 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:54:59 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023855878 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.2023855878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.1944047652
Short name T683
Test name
Test status
Simulation time 6670148031 ps
CPU time 27.08 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944047652 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.1944047652
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.3928032593
Short name T750
Test name
Test status
Simulation time 3963346848 ps
CPU time 52.06 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:57 AM UTC 24
Peak memory 221420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928032593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.3928032593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.2931684603
Short name T572
Test name
Test status
Simulation time 63824252 ps
CPU time 1.11 seconds
Started Oct 12 12:54:57 AM UTC 24
Finished Oct 12 12:55:00 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931684603 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2931684603
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.2517013087
Short name T597
Test name
Test status
Simulation time 27495034 ps
CPU time 0.98 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517013087 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.2517013087
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.93269914
Short name T595
Test name
Test status
Simulation time 43428590 ps
CPU time 0.92 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93269914 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.93269914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.2264200727
Short name T594
Test name
Test status
Simulation time 53146359 ps
CPU time 1.05 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264200727 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2264200727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.2066971513
Short name T602
Test name
Test status
Simulation time 146149192 ps
CPU time 1.43 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:07 AM UTC 24
Peak memory 211764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066971513 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.2066971513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.3604842626
Short name T587
Test name
Test status
Simulation time 38816075 ps
CPU time 1.03 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604842626 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3604842626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.3806126548
Short name T607
Test name
Test status
Simulation time 1597973128 ps
CPU time 7.14 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:12 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806126548 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3806126548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.2838488522
Short name T609
Test name
Test status
Simulation time 1453654865 ps
CPU time 10.87 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:16 AM UTC 24
Peak memory 211544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838488522 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.2838488522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.2082954167
Short name T588
Test name
Test status
Simulation time 18578723 ps
CPU time 0.88 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082954167 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.2082954167
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2722300987
Short name T598
Test name
Test status
Simulation time 62557953 ps
CPU time 1.09 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722300987
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.2722300987
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2738481644
Short name T596
Test name
Test status
Simulation time 50964614 ps
CPU time 1.1 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738481644
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.2738481644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.4199325052
Short name T586
Test name
Test status
Simulation time 28684663 ps
CPU time 0.71 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:05 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199325052 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.4199325052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.2543604747
Short name T604
Test name
Test status
Simulation time 748050999 ps
CPU time 3.58 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:09 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543604747 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2543604747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.2455559869
Short name T585
Test name
Test status
Simulation time 23684739 ps
CPU time 0.81 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:05 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455559869 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2455559869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.1536799584
Short name T745
Test name
Test status
Simulation time 5949473554 ps
CPU time 45.23 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:51 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536799584 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.1536799584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.741855407
Short name T188
Test name
Test status
Simulation time 1944520982 ps
CPU time 26.85 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 223728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741855407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.741855407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.2753688780
Short name T589
Test name
Test status
Simulation time 36560233 ps
CPU time 1.03 seconds
Started Oct 12 12:55:03 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753688780 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.2753688780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.3822101128
Short name T613
Test name
Test status
Simulation time 43012613 ps
CPU time 0.76 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822101128 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.3822101128
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2071059065
Short name T610
Test name
Test status
Simulation time 16245759 ps
CPU time 0.8 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071059065 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.2071059065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.2797950559
Short name T590
Test name
Test status
Simulation time 28123835 ps
CPU time 0.76 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797950559 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2797950559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.557441577
Short name T612
Test name
Test status
Simulation time 30894882 ps
CPU time 0.85 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557441577 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.557441577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.920474840
Short name T593
Test name
Test status
Simulation time 19845922 ps
CPU time 0.82 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920474840 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.920474840
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.1313421333
Short name T608
Test name
Test status
Simulation time 1923060693 ps
CPU time 8.05 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:13 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313421333 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1313421333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.167450282
Short name T605
Test name
Test status
Simulation time 626613542 ps
CPU time 3.67 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:09 AM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167450282 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.167450282
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.633689078
Short name T600
Test name
Test status
Simulation time 26345564 ps
CPU time 1.04 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633689078 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.633689078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2833909070
Short name T614
Test name
Test status
Simulation time 138912203 ps
CPU time 1.14 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833909070
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.2833909070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3818200341
Short name T611
Test name
Test status
Simulation time 64779465 ps
CPU time 0.92 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818200341
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.3818200341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.3998243096
Short name T591
Test name
Test status
Simulation time 20947718 ps
CPU time 0.74 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 209228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998243096 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.3998243096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.936796762
Short name T628
Test name
Test status
Simulation time 663777685 ps
CPU time 4.04 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:20 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936796762 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.936796762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.4200326845
Short name T599
Test name
Test status
Simulation time 25707121 ps
CPU time 1.06 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200326845 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.4200326845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.1711791443
Short name T631
Test name
Test status
Simulation time 1382205309 ps
CPU time 6.23 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:22 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711791443 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.1711791443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.2408872701
Short name T811
Test name
Test status
Simulation time 4530963442 ps
CPU time 62.74 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:56:19 AM UTC 24
Peak memory 221452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408872701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.2408872701
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.4144927212
Short name T601
Test name
Test status
Simulation time 159711512 ps
CPU time 1.28 seconds
Started Oct 12 12:55:04 AM UTC 24
Finished Oct 12 12:55:06 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144927212 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.4144927212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_alert_test.1963832247
Short name T624
Test name
Test status
Simulation time 50160672 ps
CPU time 0.85 seconds
Started Oct 12 12:55:16 AM UTC 24
Finished Oct 12 12:55:18 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963832247 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_alert_test.1963832247
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3923181476
Short name T619
Test name
Test status
Simulation time 24626484 ps
CPU time 0.91 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923181476 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.3923181476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_status.2604058011
Short name T617
Test name
Test status
Simulation time 15232026 ps
CPU time 0.69 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604058011 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2604058011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_div_intersig_mubi.339491368
Short name T626
Test name
Test status
Simulation time 74171180 ps
CPU time 1.14 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:18 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339491368 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.339491368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.3754856711
Short name T620
Test name
Test status
Simulation time 37770826 ps
CPU time 1.2 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754856711 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3754856711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.3632218312
Short name T630
Test name
Test status
Simulation time 1062692595 ps
CPU time 5.28 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:22 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632218312 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.3632218312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.666879327
Short name T639
Test name
Test status
Simulation time 2057634665 ps
CPU time 15.87 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666879327 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.666879327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_idle_intersig_mubi.3865008866
Short name T621
Test name
Test status
Simulation time 28326282 ps
CPU time 1.01 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865008866 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.3865008866
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.63563735
Short name T625
Test name
Test status
Simulation time 83717531 ps
CPU time 1.19 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:18 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63563735 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.63563735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.527553583
Short name T622
Test name
Test status
Simulation time 62138054 ps
CPU time 1 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527553583 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_ctrl_intersig_mubi.527553583
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.3259497882
Short name T616
Test name
Test status
Simulation time 23820081 ps
CPU time 0.76 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259497882 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.3259497882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_regwen.3658442280
Short name T632
Test name
Test status
Simulation time 1571384579 ps
CPU time 5.68 seconds
Started Oct 12 12:55:16 AM UTC 24
Finished Oct 12 12:55:22 AM UTC 24
Peak memory 211724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658442280 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.3658442280
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.4267762295
Short name T615
Test name
Test status
Simulation time 29224441 ps
CPU time 0.87 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267762295 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.4267762295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all.630744923
Short name T633
Test name
Test status
Simulation time 1288216009 ps
CPU time 6.05 seconds
Started Oct 12 12:55:16 AM UTC 24
Finished Oct 12 12:55:23 AM UTC 24
Peak memory 211960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630744923 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.630744923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.2855487830
Short name T822
Test name
Test status
Simulation time 12009995772 ps
CPU time 71.01 seconds
Started Oct 12 12:55:16 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 221820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855487830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2855487830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.1376569094
Short name T618
Test name
Test status
Simulation time 90002157 ps
CPU time 1.07 seconds
Started Oct 12 12:55:15 AM UTC 24
Finished Oct 12 12:55:17 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376569094 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1376569094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.3306339682
Short name T638
Test name
Test status
Simulation time 20710320 ps
CPU time 0.83 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306339682 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.3306339682
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.4169092273
Short name T641
Test name
Test status
Simulation time 31101438 ps
CPU time 1.07 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169092273 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.4169092273
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.2165645693
Short name T635
Test name
Test status
Simulation time 27382114 ps
CPU time 0.72 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:23 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165645693 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2165645693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.2757937795
Short name T640
Test name
Test status
Simulation time 37841435 ps
CPU time 0.91 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757937795 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.2757937795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.3256411593
Short name T623
Test name
Test status
Simulation time 24339752 ps
CPU time 0.79 seconds
Started Oct 12 12:55:16 AM UTC 24
Finished Oct 12 12:55:18 AM UTC 24
Peak memory 211628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256411593 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3256411593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.515278624
Short name T659
Test name
Test status
Simulation time 1533690940 ps
CPU time 8.62 seconds
Started Oct 12 12:55:16 AM UTC 24
Finished Oct 12 12:55:25 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515278624 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.515278624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.2934159897
Short name T662
Test name
Test status
Simulation time 616948220 ps
CPU time 5.04 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:28 AM UTC 24
Peak memory 211804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934159897 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.2934159897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.3393738621
Short name T637
Test name
Test status
Simulation time 30810945 ps
CPU time 0.87 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393738621 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.3393738621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3211663217
Short name T644
Test name
Test status
Simulation time 46967171 ps
CPU time 0.99 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211663217
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.3211663217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1890903796
Short name T646
Test name
Test status
Simulation time 100852431 ps
CPU time 1.26 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890903796
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.1890903796
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.984481007
Short name T634
Test name
Test status
Simulation time 32361009 ps
CPU time 0.72 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:23 AM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984481007 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.984481007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.32626281
Short name T660
Test name
Test status
Simulation time 649123798 ps
CPU time 4.02 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:27 AM UTC 24
Peak memory 211672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32626281 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.32626281
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.1395190049
Short name T627
Test name
Test status
Simulation time 158458890 ps
CPU time 1.26 seconds
Started Oct 12 12:55:16 AM UTC 24
Finished Oct 12 12:55:18 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395190049 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1395190049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.4289340734
Short name T657
Test name
Test status
Simulation time 123404938 ps
CPU time 1.52 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289340734 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.4289340734
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.2145105791
Short name T853
Test name
Test status
Simulation time 26685748765 ps
CPU time 153.57 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:57:58 AM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145105791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.2145105791
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.2041395938
Short name T636
Test name
Test status
Simulation time 57266263 ps
CPU time 1 seconds
Started Oct 12 12:55:21 AM UTC 24
Finished Oct 12 12:55:23 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041395938 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2041395938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.436512068
Short name T665
Test name
Test status
Simulation time 49423233 ps
CPU time 0.86 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436512068 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.436512068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.405801592
Short name T655
Test name
Test status
Simulation time 29560717 ps
CPU time 0.88 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405801592 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.405801592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.2852904563
Short name T649
Test name
Test status
Simulation time 17004383 ps
CPU time 0.75 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852904563 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2852904563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.4046271124
Short name T651
Test name
Test status
Simulation time 18071854 ps
CPU time 0.81 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046271124 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.4046271124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.2666338282
Short name T647
Test name
Test status
Simulation time 13588868 ps
CPU time 0.87 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666338282 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2666338282
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.4095086882
Short name T688
Test name
Test status
Simulation time 1636334749 ps
CPU time 12.63 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:36 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095086882 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.4095086882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.138110575
Short name T664
Test name
Test status
Simulation time 1361816793 ps
CPU time 5.64 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:29 AM UTC 24
Peak memory 211808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138110575 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.138110575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.3842504724
Short name T653
Test name
Test status
Simulation time 73534145 ps
CPU time 1 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842504724 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.3842504724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1551105045
Short name T650
Test name
Test status
Simulation time 23629212 ps
CPU time 0.75 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551105045
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.1551105045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3548778898
Short name T652
Test name
Test status
Simulation time 65570704 ps
CPU time 0.93 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548778898
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.3548778898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.277232196
Short name T648
Test name
Test status
Simulation time 19165996 ps
CPU time 0.9 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277232196 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.277232196
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.2608196700
Short name T658
Test name
Test status
Simulation time 280193482 ps
CPU time 2.07 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:25 AM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608196700 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2608196700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.4211638058
Short name T645
Test name
Test status
Simulation time 23875988 ps
CPU time 0.88 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211638058 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.4211638058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.1337069463
Short name T754
Test name
Test status
Simulation time 5488634752 ps
CPU time 29.54 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:56:00 AM UTC 24
Peak memory 211568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337069463 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1337069463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.1717606704
Short name T839
Test name
Test status
Simulation time 8126846485 ps
CPU time 67.45 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:56:38 AM UTC 24
Peak memory 221752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717606704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1717606704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.4107074104
Short name T654
Test name
Test status
Simulation time 31065341 ps
CPU time 1.06 seconds
Started Oct 12 12:55:22 AM UTC 24
Finished Oct 12 12:55:24 AM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107074104 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.4107074104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_alert_test.2034641358
Short name T675
Test name
Test status
Simulation time 14592450 ps
CPU time 0.81 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034641358 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_alert_test.2034641358
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.398512514
Short name T673
Test name
Test status
Simulation time 77034675 ps
CPU time 1.08 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398512514 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.398512514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.2394963179
Short name T667
Test name
Test status
Simulation time 18916044 ps
CPU time 0.78 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394963179 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2394963179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_div_intersig_mubi.4077917891
Short name T674
Test name
Test status
Simulation time 30736239 ps
CPU time 1.12 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077917891 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.4077917891
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.1294343845
Short name T668
Test name
Test status
Simulation time 67572905 ps
CPU time 1.01 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294343845 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1294343845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.4278744945
Short name T710
Test name
Test status
Simulation time 2553457720 ps
CPU time 9.82 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:40 AM UTC 24
Peak memory 211808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278744945 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.4278744945
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.3418688878
Short name T707
Test name
Test status
Simulation time 1217693802 ps
CPU time 9.47 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:40 AM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418688878 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.3418688878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.2147978416
Short name T677
Test name
Test status
Simulation time 153138169 ps
CPU time 1.32 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147978416 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.2147978416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2397393543
Short name T676
Test name
Test status
Simulation time 83867954 ps
CPU time 1.1 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397393543
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_clk_byp_req_intersig_mubi.2397393543
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.2464064179
Short name T671
Test name
Test status
Simulation time 44566063 ps
CPU time 0.98 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464064179
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_ctrl_intersig_mubi.2464064179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.1466989811
Short name T666
Test name
Test status
Simulation time 15914456 ps
CPU time 0.72 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466989811 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1466989811
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_regwen.2315620580
Short name T672
Test name
Test status
Simulation time 89863610 ps
CPU time 0.94 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315620580 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.2315620580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.17551872
Short name T669
Test name
Test status
Simulation time 95722649 ps
CPU time 1.07 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17551872 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.17551872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all.2090329524
Short name T777
Test name
Test status
Simulation time 8819680750 ps
CPU time 36.07 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:56:07 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090329524 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.2090329524
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.3397011302
Short name T744
Test name
Test status
Simulation time 2351920337 ps
CPU time 19.61 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:50 AM UTC 24
Peak memory 225532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397011302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3397011302
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/39.clkmgr_trans.779563759
Short name T670
Test name
Test status
Simulation time 30698359 ps
CPU time 0.88 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:31 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779563759 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.779563759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/39.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.1111724832
Short name T224
Test name
Test status
Simulation time 24908787 ps
CPU time 0.81 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111724832 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.1111724832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.3126572907
Short name T80
Test name
Test status
Simulation time 36557026 ps
CPU time 1.1 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126572907 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.3126572907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.351580832
Short name T199
Test name
Test status
Simulation time 14417947 ps
CPU time 0.69 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351580832 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.351580832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.4228299682
Short name T169
Test name
Test status
Simulation time 25619885 ps
CPU time 0.87 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228299682 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.4228299682
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.923551257
Short name T168
Test name
Test status
Simulation time 21180198 ps
CPU time 0.83 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923551257 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.923551257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.2697434714
Short name T10
Test name
Test status
Simulation time 1286537166 ps
CPU time 7.46 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:53:03 AM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697434714 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2697434714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.2322893442
Short name T102
Test name
Test status
Simulation time 2029431350 ps
CPU time 6.72 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322893442 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.2322893442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.3047305625
Short name T214
Test name
Test status
Simulation time 52176570 ps
CPU time 1.14 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047305625 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.3047305625
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2961639097
Short name T119
Test name
Test status
Simulation time 33178200 ps
CPU time 0.86 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961639097
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.2961639097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1682020094
Short name T221
Test name
Test status
Simulation time 45119097 ps
CPU time 0.83 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682020094
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.1682020094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.2246158499
Short name T220
Test name
Test status
Simulation time 19390739 ps
CPU time 0.75 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246158499 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.2246158499
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.335384263
Short name T46
Test name
Test status
Simulation time 426324977 ps
CPU time 2.16 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335384263 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.335384263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.2337389899
Short name T110
Test name
Test status
Simulation time 285044462 ps
CPU time 3.31 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:59 AM UTC 24
Peak memory 244160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337389899 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.2337389899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.1222696268
Short name T218
Test name
Test status
Simulation time 112017456 ps
CPU time 1.05 seconds
Started Oct 12 12:52:52 AM UTC 24
Finished Oct 12 12:52:54 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222696268 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1222696268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.1135809540
Short name T8
Test name
Test status
Simulation time 1411586680 ps
CPU time 6.57 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:53:03 AM UTC 24
Peak memory 211796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135809540 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.1135809540
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.4226325567
Short name T55
Test name
Test status
Simulation time 5478438282 ps
CPU time 32.1 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:53:29 AM UTC 24
Peak memory 221440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226325567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.4226325567
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.3981031974
Short name T222
Test name
Test status
Simulation time 85655640 ps
CPU time 1.06 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981031974 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3981031974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.3953375164
Short name T691
Test name
Test status
Simulation time 27309359 ps
CPU time 0.92 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:38 AM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953375164 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.3953375164
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1908494187
Short name T690
Test name
Test status
Simulation time 21755763 ps
CPU time 0.89 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:38 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908494187 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.1908494187
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_status.2725307199
Short name T680
Test name
Test status
Simulation time 30388861 ps
CPU time 0.82 seconds
Started Oct 12 12:55:30 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725307199 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.2725307199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_div_intersig_mubi.880179660
Short name T689
Test name
Test status
Simulation time 24936983 ps
CPU time 0.75 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:38 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880179660 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.880179660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_extclk.1787590001
Short name T679
Test name
Test status
Simulation time 25446724 ps
CPU time 0.94 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787590001 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1787590001
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency.330513641
Short name T709
Test name
Test status
Simulation time 2522898295 ps
CPU time 8.99 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:40 AM UTC 24
Peak memory 211856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330513641 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.330513641
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency_timeout.2169751244
Short name T643
Test name
Test status
Simulation time 159776429 ps
CPU time 1.2 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169751244 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_timeout.2169751244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_idle_intersig_mubi.3451020321
Short name T684
Test name
Test status
Simulation time 46108147 ps
CPU time 0.97 seconds
Started Oct 12 12:55:30 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451020321 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3451020321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.39170627
Short name T682
Test name
Test status
Simulation time 55113173 ps
CPU time 0.85 seconds
Started Oct 12 12:55:30 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39170627 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_clk_byp_req_intersig_mubi.39170627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.1242474290
Short name T685
Test name
Test status
Simulation time 67777726 ps
CPU time 1.01 seconds
Started Oct 12 12:55:30 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242474290
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_ctrl_intersig_mubi.1242474290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_peri.1925067903
Short name T681
Test name
Test status
Simulation time 16835426 ps
CPU time 0.89 seconds
Started Oct 12 12:55:30 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925067903 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1925067903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.4219957437
Short name T714
Test name
Test status
Simulation time 1270158492 ps
CPU time 4.64 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:42 AM UTC 24
Peak memory 211724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219957437 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.4219957437
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_smoke.828358123
Short name T678
Test name
Test status
Simulation time 78737202 ps
CPU time 1.06 seconds
Started Oct 12 12:55:29 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828358123 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.828358123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.62743126
Short name T712
Test name
Test status
Simulation time 814024028 ps
CPU time 3.94 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:41 AM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62743126 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.62743126
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.170004162
Short name T717
Test name
Test status
Simulation time 487044281 ps
CPU time 9.5 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:47 AM UTC 24
Peak memory 221388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170004162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.170004162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/40.clkmgr_trans.3915625205
Short name T642
Test name
Test status
Simulation time 86785781 ps
CPU time 1.1 seconds
Started Oct 12 12:55:30 AM UTC 24
Finished Oct 12 12:55:32 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915625205 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3915625205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/40.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.3467039724
Short name T699
Test name
Test status
Simulation time 18934884 ps
CPU time 0.94 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467039724 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.3467039724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.674981562
Short name T698
Test name
Test status
Simulation time 25807640 ps
CPU time 1.09 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674981562 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.674981562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.3751758283
Short name T697
Test name
Test status
Simulation time 46435420 ps
CPU time 0.89 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751758283 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3751758283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.3127692674
Short name T696
Test name
Test status
Simulation time 15720786 ps
CPU time 0.73 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127692674 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.3127692674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.2440926032
Short name T692
Test name
Test status
Simulation time 29386536 ps
CPU time 0.91 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:38 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440926032 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.2440926032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency.195934508
Short name T713
Test name
Test status
Simulation time 563141785 ps
CPU time 3.81 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:41 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195934508 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.195934508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency_timeout.2592797301
Short name T715
Test name
Test status
Simulation time 1917631034 ps
CPU time 5.98 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:44 AM UTC 24
Peak memory 211608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592797301 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_timeout.2592797301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.3213805924
Short name T703
Test name
Test status
Simulation time 131900651 ps
CPU time 1.37 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213805924 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.3213805924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.596967374
Short name T702
Test name
Test status
Simulation time 27587308 ps
CPU time 1.21 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596967374 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.596967374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3663907547
Short name T694
Test name
Test status
Simulation time 34412832 ps
CPU time 0.82 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663907547
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.3663907547
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.2064899406
Short name T693
Test name
Test status
Simulation time 15467965 ps
CPU time 0.83 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 209228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064899406 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2064899406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.4121095803
Short name T711
Test name
Test status
Simulation time 421133497 ps
CPU time 2.78 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:41 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121095803 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.4121095803
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.2558124594
Short name T695
Test name
Test status
Simulation time 39673261 ps
CPU time 1.03 seconds
Started Oct 12 12:55:36 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558124594 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2558124594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.1129955814
Short name T108
Test name
Test status
Simulation time 21208387840 ps
CPU time 82.94 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:57:02 AM UTC 24
Peak memory 211828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129955814 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.1129955814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.1827897417
Short name T834
Test name
Test status
Simulation time 3210994881 ps
CPU time 50.89 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 221696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827897417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.1827897417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.2737024331
Short name T708
Test name
Test status
Simulation time 236092111 ps
CPU time 1.81 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:40 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737024331 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2737024331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.21455441
Short name T723
Test name
Test status
Simulation time 59476944 ps
CPU time 0.83 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:48 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21455441 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.21455441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2692525048
Short name T719
Test name
Test status
Simulation time 20424566 ps
CPU time 0.84 seconds
Started Oct 12 12:55:46 AM UTC 24
Finished Oct 12 12:55:48 AM UTC 24
Peak memory 211776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692525048 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.2692525048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.1245207374
Short name T705
Test name
Test status
Simulation time 32841848 ps
CPU time 0.86 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245207374 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.1245207374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.1667077387
Short name T731
Test name
Test status
Simulation time 86305071 ps
CPU time 1.14 seconds
Started Oct 12 12:55:46 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667077387 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.1667077387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.1736975916
Short name T704
Test name
Test status
Simulation time 74246937 ps
CPU time 1.07 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736975916 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1736975916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.1360710989
Short name T724
Test name
Test status
Simulation time 2417625606 ps
CPU time 10.13 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:48 AM UTC 24
Peak memory 211808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360710989 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1360710989
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.4280083896
Short name T716
Test name
Test status
Simulation time 864187889 ps
CPU time 6.24 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:45 AM UTC 24
Peak memory 211804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280083896 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.4280083896
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.4220516606
Short name T720
Test name
Test status
Simulation time 67903838 ps
CPU time 0.97 seconds
Started Oct 12 12:55:46 AM UTC 24
Finished Oct 12 12:55:48 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220516606 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.4220516606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1287196905
Short name T725
Test name
Test status
Simulation time 188943305 ps
CPU time 1.17 seconds
Started Oct 12 12:55:46 AM UTC 24
Finished Oct 12 12:55:48 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287196905
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.1287196905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3226759449
Short name T718
Test name
Test status
Simulation time 23187272 ps
CPU time 0.79 seconds
Started Oct 12 12:55:46 AM UTC 24
Finished Oct 12 12:55:48 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226759449
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.3226759449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.1401424179
Short name T701
Test name
Test status
Simulation time 36752645 ps
CPU time 0.79 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401424179 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1401424179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.2503101875
Short name T748
Test name
Test status
Simulation time 856808145 ps
CPU time 5.03 seconds
Started Oct 12 12:55:46 AM UTC 24
Finished Oct 12 12:55:53 AM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503101875 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2503101875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.2341994029
Short name T700
Test name
Test status
Simulation time 21083590 ps
CPU time 0.86 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:39 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341994029 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2341994029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.3367757033
Short name T845
Test name
Test status
Simulation time 7530064091 ps
CPU time 55.62 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:56:44 AM UTC 24
Peak memory 211888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367757033 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.3367757033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.881475226
Short name T840
Test name
Test status
Simulation time 4637696718 ps
CPU time 50.25 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:56:38 AM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881475226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.881475226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.1597671983
Short name T706
Test name
Test status
Simulation time 71442236 ps
CPU time 1.22 seconds
Started Oct 12 12:55:37 AM UTC 24
Finished Oct 12 12:55:40 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597671983 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1597671983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.2083105753
Short name T740
Test name
Test status
Simulation time 21561695 ps
CPU time 0.84 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083105753 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.2083105753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2689625347
Short name T733
Test name
Test status
Simulation time 17549711 ps
CPU time 0.76 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689625347 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.2689625347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.286705503
Short name T732
Test name
Test status
Simulation time 26876682 ps
CPU time 0.81 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286705503 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.286705503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.77842289
Short name T739
Test name
Test status
Simulation time 22128024 ps
CPU time 0.97 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77842289 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.77842289
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.410422024
Short name T726
Test name
Test status
Simulation time 25849550 ps
CPU time 0.86 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410422024 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.410422024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.1172969886
Short name T747
Test name
Test status
Simulation time 946674009 ps
CPU time 3.86 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:52 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172969886 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1172969886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.1803890159
Short name T741
Test name
Test status
Simulation time 146789192 ps
CPU time 1.35 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803890159 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.1803890159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.1063664175
Short name T736
Test name
Test status
Simulation time 28181056 ps
CPU time 1.03 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063664175 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.1063664175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2217881464
Short name T734
Test name
Test status
Simulation time 21752805 ps
CPU time 0.83 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217881464
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.2217881464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.683345756
Short name T737
Test name
Test status
Simulation time 84716370 ps
CPU time 1.02 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683345756 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.683345756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.3542023677
Short name T735
Test name
Test status
Simulation time 22254625 ps
CPU time 1.03 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 209220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542023677 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3542023677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.3469720041
Short name T746
Test name
Test status
Simulation time 647833479 ps
CPU time 2.92 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:51 AM UTC 24
Peak memory 211668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469720041 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3469720041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.2541477782
Short name T727
Test name
Test status
Simulation time 42870359 ps
CPU time 0.94 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541477782 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2541477782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.3290825555
Short name T781
Test name
Test status
Simulation time 5527625436 ps
CPU time 22.5 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:56:11 AM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290825555 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.3290825555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.2768046182
Short name T846
Test name
Test status
Simulation time 3144528959 ps
CPU time 55.82 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:56:45 AM UTC 24
Peak memory 221440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768046182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.2768046182
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.1549581643
Short name T729
Test name
Test status
Simulation time 52819240 ps
CPU time 0.84 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549581643 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1549581643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.1689245584
Short name T728
Test name
Test status
Simulation time 72669960 ps
CPU time 0.94 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689245584 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.1689245584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.4256610083
Short name T759
Test name
Test status
Simulation time 19532892 ps
CPU time 0.78 seconds
Started Oct 12 12:55:59 AM UTC 24
Finished Oct 12 12:56:01 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256610083 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.4256610083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.1450733940
Short name T756
Test name
Test status
Simulation time 14652114 ps
CPU time 0.7 seconds
Started Oct 12 12:55:59 AM UTC 24
Finished Oct 12 12:56:01 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450733940 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.1450733940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.1320703245
Short name T722
Test name
Test status
Simulation time 93967888 ps
CPU time 0.97 seconds
Started Oct 12 12:55:59 AM UTC 24
Finished Oct 12 12:56:01 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320703245 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.1320703245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.2305499957
Short name T743
Test name
Test status
Simulation time 20827815 ps
CPU time 0.97 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305499957 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.2305499957
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.2763310423
Short name T752
Test name
Test status
Simulation time 1279084623 ps
CPU time 10.44 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:59 AM UTC 24
Peak memory 211484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763310423 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2763310423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.2580710423
Short name T749
Test name
Test status
Simulation time 1951139206 ps
CPU time 7.84 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:56 AM UTC 24
Peak memory 211800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580710423 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.2580710423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.279734874
Short name T757
Test name
Test status
Simulation time 17676473 ps
CPU time 0.75 seconds
Started Oct 12 12:55:59 AM UTC 24
Finished Oct 12 12:56:01 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279734874 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.279734874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1641207592
Short name T760
Test name
Test status
Simulation time 85825316 ps
CPU time 1 seconds
Started Oct 12 12:55:59 AM UTC 24
Finished Oct 12 12:56:01 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641207592
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.1641207592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3031428330
Short name T758
Test name
Test status
Simulation time 23320867 ps
CPU time 0.79 seconds
Started Oct 12 12:55:59 AM UTC 24
Finished Oct 12 12:56:01 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031428330
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.3031428330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.856063789
Short name T738
Test name
Test status
Simulation time 22126612 ps
CPU time 0.76 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856063789 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.856063789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.826773865
Short name T775
Test name
Test status
Simulation time 551228054 ps
CPU time 2.64 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:03 AM UTC 24
Peak memory 211988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826773865 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.826773865
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.2378726753
Short name T742
Test name
Test status
Simulation time 57832839 ps
CPU time 0.93 seconds
Started Oct 12 12:55:47 AM UTC 24
Finished Oct 12 12:55:49 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378726753 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.2378726753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.598229741
Short name T835
Test name
Test status
Simulation time 8146287780 ps
CPU time 31.47 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:32 AM UTC 24
Peak memory 211860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598229741 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.598229741
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.694714206
Short name T847
Test name
Test status
Simulation time 4860342861 ps
CPU time 66.5 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:57:08 AM UTC 24
Peak memory 225200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694714206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.694714206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.3846939930
Short name T721
Test name
Test status
Simulation time 37111841 ps
CPU time 1 seconds
Started Oct 12 12:55:59 AM UTC 24
Finished Oct 12 12:56:01 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846939930 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3846939930
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.3155711487
Short name T771
Test name
Test status
Simulation time 60041214 ps
CPU time 0.99 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155711487 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.3155711487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.243926176
Short name T768
Test name
Test status
Simulation time 30270598 ps
CPU time 0.94 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243926176 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.243926176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.872397525
Short name T764
Test name
Test status
Simulation time 28960975 ps
CPU time 0.76 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872397525 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.872397525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.2683667832
Short name T769
Test name
Test status
Simulation time 18900855 ps
CPU time 0.93 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683667832 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.2683667832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.3138977432
Short name T763
Test name
Test status
Simulation time 36636497 ps
CPU time 0.87 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138977432 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.3138977432
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.984014350
Short name T778
Test name
Test status
Simulation time 1786996772 ps
CPU time 7.98 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:09 AM UTC 24
Peak memory 211792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984014350 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.984014350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.2565102491
Short name T776
Test name
Test status
Simulation time 636768640 ps
CPU time 3.1 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:04 AM UTC 24
Peak memory 211804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565102491 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.2565102491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.353423145
Short name T774
Test name
Test status
Simulation time 402552237 ps
CPU time 2.05 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:03 AM UTC 24
Peak memory 211456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353423145 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.353423145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.2629650369
Short name T767
Test name
Test status
Simulation time 51969045 ps
CPU time 1.04 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629650369
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.2629650369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.246254656
Short name T766
Test name
Test status
Simulation time 56675166 ps
CPU time 0.91 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246254656 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.246254656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.657097802
Short name T730
Test name
Test status
Simulation time 16996414 ps
CPU time 0.82 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657097802 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.657097802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.2264494837
Short name T773
Test name
Test status
Simulation time 60146379 ps
CPU time 1.28 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:03 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264494837 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2264494837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.319351147
Short name T761
Test name
Test status
Simulation time 21410908 ps
CPU time 0.81 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319351147 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.319351147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.271305205
Short name T851
Test name
Test status
Simulation time 11198868288 ps
CPU time 80.15 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:57:22 AM UTC 24
Peak memory 212096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271305205 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.271305205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.2666451051
Short name T809
Test name
Test status
Simulation time 938605195 ps
CPU time 15.61 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:17 AM UTC 24
Peak memory 221372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666451051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.2666451051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.1151295285
Short name T765
Test name
Test status
Simulation time 31977103 ps
CPU time 0.96 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151295285 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1151295285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.2010055021
Short name T790
Test name
Test status
Simulation time 50305239 ps
CPU time 0.87 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010055021 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.2010055021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2137528211
Short name T789
Test name
Test status
Simulation time 95042485 ps
CPU time 1.06 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137528211 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.2137528211
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.760886351
Short name T786
Test name
Test status
Simulation time 150396836 ps
CPU time 1.06 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760886351 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.760886351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.3693942505
Short name T787
Test name
Test status
Simulation time 65540225 ps
CPU time 0.87 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693942505 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.3693942505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.1295827150
Short name T772
Test name
Test status
Simulation time 25393679 ps
CPU time 0.94 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295827150 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1295827150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.2475180859
Short name T779
Test name
Test status
Simulation time 2171856024 ps
CPU time 7.73 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:09 AM UTC 24
Peak memory 211864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475180859 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.2475180859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.40759904
Short name T808
Test name
Test status
Simulation time 1030800485 ps
CPU time 4.85 seconds
Started Oct 12 12:56:10 AM UTC 24
Finished Oct 12 12:56:16 AM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40759904 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.40759904
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.80374382
Short name T785
Test name
Test status
Simulation time 26201849 ps
CPU time 0.89 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80374382 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.80374382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.4166545541
Short name T792
Test name
Test status
Simulation time 64519346 ps
CPU time 1.06 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166545541
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.4166545541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3282712531
Short name T784
Test name
Test status
Simulation time 13155822 ps
CPU time 0.72 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:12 AM UTC 24
Peak memory 211192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282712531
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.3282712531
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.260395060
Short name T782
Test name
Test status
Simulation time 15235275 ps
CPU time 0.76 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:12 AM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260395060 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.260395060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.4282767976
Short name T770
Test name
Test status
Simulation time 56545865 ps
CPU time 0.88 seconds
Started Oct 12 12:56:00 AM UTC 24
Finished Oct 12 12:56:02 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282767976 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.4282767976
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.1927200898
Short name T842
Test name
Test status
Simulation time 7448604603 ps
CPU time 28.53 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:41 AM UTC 24
Peak memory 211836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927200898 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1927200898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.45195398
Short name T850
Test name
Test status
Simulation time 6630359377 ps
CPU time 64.11 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:57:17 AM UTC 24
Peak memory 221480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45195398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.45195398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.4080032457
Short name T783
Test name
Test status
Simulation time 21414363 ps
CPU time 0.83 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:12 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080032457 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.4080032457
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.1537573997
Short name T804
Test name
Test status
Simulation time 122034117 ps
CPU time 1.06 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:14 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537573997 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.1537573997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2701048002
Short name T798
Test name
Test status
Simulation time 42127522 ps
CPU time 0.83 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701048002 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.2701048002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.2614634279
Short name T793
Test name
Test status
Simulation time 38292177 ps
CPU time 0.84 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614634279 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2614634279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.1108486895
Short name T796
Test name
Test status
Simulation time 15775876 ps
CPU time 0.72 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108486895 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.1108486895
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.3160311292
Short name T791
Test name
Test status
Simulation time 18278463 ps
CPU time 0.79 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160311292 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3160311292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.1209159124
Short name T810
Test name
Test status
Simulation time 795617967 ps
CPU time 6.55 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:19 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209159124 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1209159124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.1876866225
Short name T812
Test name
Test status
Simulation time 979295782 ps
CPU time 7.29 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:20 AM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876866225 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.1876866225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.3732526606
Short name T799
Test name
Test status
Simulation time 67688427 ps
CPU time 1 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732526606 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.3732526606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3000876594
Short name T794
Test name
Test status
Simulation time 12570369 ps
CPU time 0.73 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000876594
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.3000876594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.461443691
Short name T795
Test name
Test status
Simulation time 16509433 ps
CPU time 0.78 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461443691 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.461443691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.2455169424
Short name T797
Test name
Test status
Simulation time 27606987 ps
CPU time 1 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455169424 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2455169424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.4213162148
Short name T807
Test name
Test status
Simulation time 733718751 ps
CPU time 3.34 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:16 AM UTC 24
Peak memory 211724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213162148 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.4213162148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.2174688265
Short name T788
Test name
Test status
Simulation time 19068703 ps
CPU time 0.79 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174688265 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2174688265
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.406293683
Short name T806
Test name
Test status
Simulation time 193421849 ps
CPU time 2.29 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:15 AM UTC 24
Peak memory 211680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406293683 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.406293683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.1986383933
Short name T841
Test name
Test status
Simulation time 2908497852 ps
CPU time 26.63 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:39 AM UTC 24
Peak memory 221728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986383933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.1986383933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.1919098162
Short name T800
Test name
Test status
Simulation time 56677259 ps
CPU time 1.14 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919098162 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1919098162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.504000471
Short name T823
Test name
Test status
Simulation time 28290470 ps
CPU time 0.82 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504000471 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.504000471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2000730049
Short name T818
Test name
Test status
Simulation time 24964867 ps
CPU time 0.76 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000730049 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.2000730049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.4236782924
Short name T815
Test name
Test status
Simulation time 12413339 ps
CPU time 0.64 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236782924 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.4236782924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.2261639015
Short name T819
Test name
Test status
Simulation time 42389195 ps
CPU time 0.83 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261639015 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.2261639015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.2760547127
Short name T801
Test name
Test status
Simulation time 27033725 ps
CPU time 0.85 seconds
Started Oct 12 12:56:12 AM UTC 24
Finished Oct 12 12:56:13 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760547127 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2760547127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.1713808967
Short name T813
Test name
Test status
Simulation time 915450066 ps
CPU time 7.58 seconds
Started Oct 12 12:56:12 AM UTC 24
Finished Oct 12 12:56:20 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713808967 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1713808967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.4288667290
Short name T814
Test name
Test status
Simulation time 1942481691 ps
CPU time 9.87 seconds
Started Oct 12 12:56:12 AM UTC 24
Finished Oct 12 12:56:23 AM UTC 24
Peak memory 211800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288667290 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.4288667290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.4230117692
Short name T820
Test name
Test status
Simulation time 73949992 ps
CPU time 1.07 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230117692 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.4230117692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1337817241
Short name T817
Test name
Test status
Simulation time 20206640 ps
CPU time 0.75 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337817241
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.1337817241
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1852728096
Short name T816
Test name
Test status
Simulation time 27227741 ps
CPU time 0.76 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852728096
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.1852728096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.1662801960
Short name T803
Test name
Test status
Simulation time 14925020 ps
CPU time 0.87 seconds
Started Oct 12 12:56:12 AM UTC 24
Finished Oct 12 12:56:14 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662801960 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1662801960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.1302826767
Short name T829
Test name
Test status
Simulation time 275236491 ps
CPU time 1.53 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302826767 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1302826767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.2915438283
Short name T802
Test name
Test status
Simulation time 22181895 ps
CPU time 0.96 seconds
Started Oct 12 12:56:11 AM UTC 24
Finished Oct 12 12:56:14 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915438283 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2915438283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3170642510
Short name T849
Test name
Test status
Simulation time 5954787757 ps
CPU time 45.1 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:57:13 AM UTC 24
Peak memory 211832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170642510 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.3170642510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.2457739280
Short name T848
Test name
Test status
Simulation time 7259069415 ps
CPU time 43.12 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:57:11 AM UTC 24
Peak memory 225596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457739280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2457739280
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.1948694035
Short name T805
Test name
Test status
Simulation time 78576009 ps
CPU time 1.09 seconds
Started Oct 12 12:56:12 AM UTC 24
Finished Oct 12 12:56:14 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948694035 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1948694035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.2534297874
Short name T832
Test name
Test status
Simulation time 17003430 ps
CPU time 0.77 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534297874 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.2534297874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2621951935
Short name T762
Test name
Test status
Simulation time 23188222 ps
CPU time 0.99 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621951935 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.2621951935
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.995636761
Short name T826
Test name
Test status
Simulation time 13132107 ps
CPU time 0.7 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995636761 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.995636761
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.499804315
Short name T831
Test name
Test status
Simulation time 80896976 ps
CPU time 0.98 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499804315 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.499804315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.275852174
Short name T824
Test name
Test status
Simulation time 263051953 ps
CPU time 1.43 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275852174 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.275852174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.2265624974
Short name T843
Test name
Test status
Simulation time 1636539799 ps
CPU time 13.57 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:41 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265624974 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2265624974
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.3758302790
Short name T836
Test name
Test status
Simulation time 1114426384 ps
CPU time 4.85 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:33 AM UTC 24
Peak memory 211548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758302790 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.3758302790
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.2857772316
Short name T833
Test name
Test status
Simulation time 37364339 ps
CPU time 1.11 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857772316 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.2857772316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3611543968
Short name T827
Test name
Test status
Simulation time 10604794 ps
CPU time 0.94 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611543968
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.3611543968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2288547527
Short name T828
Test name
Test status
Simulation time 14523584 ps
CPU time 0.89 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288547527
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.2288547527
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.3422659293
Short name T825
Test name
Test status
Simulation time 27295548 ps
CPU time 0.73 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422659293 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3422659293
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.3652741369
Short name T838
Test name
Test status
Simulation time 1186225454 ps
CPU time 6.69 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:35 AM UTC 24
Peak memory 211692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652741369 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3652741369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.3044400889
Short name T821
Test name
Test status
Simulation time 20776055 ps
CPU time 0.83 seconds
Started Oct 12 12:56:26 AM UTC 24
Finished Oct 12 12:56:28 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044400889 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3044400889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.2557147915
Short name T844
Test name
Test status
Simulation time 3205737329 ps
CPU time 15.06 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:43 AM UTC 24
Peak memory 211888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557147915 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.2557147915
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.796637056
Short name T852
Test name
Test status
Simulation time 3338940264 ps
CPU time 62.85 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:57:32 AM UTC 24
Peak memory 221488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796637056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.796637056
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.3489449647
Short name T830
Test name
Test status
Simulation time 77316291 ps
CPU time 1.08 seconds
Started Oct 12 12:56:27 AM UTC 24
Finished Oct 12 12:56:29 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489449647 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3489449647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.703882328
Short name T177
Test name
Test status
Simulation time 20940344 ps
CPU time 0.92 seconds
Started Oct 12 12:52:57 AM UTC 24
Finished Oct 12 12:52:59 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703882328 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.703882328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2799229286
Short name T92
Test name
Test status
Simulation time 25938455 ps
CPU time 0.95 seconds
Started Oct 12 12:52:56 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799229286 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.2799229286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.3129109072
Short name T200
Test name
Test status
Simulation time 98268208 ps
CPU time 0.99 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129109072 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.3129109072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.2946766108
Short name T227
Test name
Test status
Simulation time 62690623 ps
CPU time 1.03 seconds
Started Oct 12 12:52:56 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946766108 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.2946766108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.949725485
Short name T29
Test name
Test status
Simulation time 24259029 ps
CPU time 0.99 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949725485 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.949725485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.4214986800
Short name T12
Test name
Test status
Simulation time 1404625389 ps
CPU time 8.53 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:53:05 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214986800 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.4214986800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.1991140528
Short name T256
Test name
Test status
Simulation time 1580846390 ps
CPU time 12.18 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:53:09 AM UTC 24
Peak memory 211496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991140528 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.1991140528
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.3265659161
Short name T225
Test name
Test status
Simulation time 36489350 ps
CPU time 0.92 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265659161 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.3265659161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.610072770
Short name T170
Test name
Test status
Simulation time 22299526 ps
CPU time 0.85 seconds
Started Oct 12 12:52:56 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610072770 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.610072770
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.158380764
Short name T226
Test name
Test status
Simulation time 16683370 ps
CPU time 1.01 seconds
Started Oct 12 12:52:56 AM UTC 24
Finished Oct 12 12:52:58 AM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158380764 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.158380764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.398373088
Short name T223
Test name
Test status
Simulation time 32999443 ps
CPU time 0.9 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398373088 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.398373088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.1710758042
Short name T52
Test name
Test status
Simulation time 760656867 ps
CPU time 2.81 seconds
Started Oct 12 12:52:56 AM UTC 24
Finished Oct 12 12:53:00 AM UTC 24
Peak memory 211676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710758042 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1710758042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.4216356025
Short name T219
Test name
Test status
Simulation time 41961350 ps
CPU time 0.9 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216356025 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.4216356025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.2543332141
Short name T386
Test name
Test status
Simulation time 8998748863 ps
CPU time 47.69 seconds
Started Oct 12 12:52:56 AM UTC 24
Finished Oct 12 12:53:45 AM UTC 24
Peak memory 211832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543332141 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.2543332141
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.1524310080
Short name T184
Test name
Test status
Simulation time 32199140886 ps
CPU time 112.35 seconds
Started Oct 12 12:52:56 AM UTC 24
Finished Oct 12 12:54:50 AM UTC 24
Peak memory 221464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524310080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1524310080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.2714392147
Short name T136
Test name
Test status
Simulation time 13189675 ps
CPU time 0.81 seconds
Started Oct 12 12:52:55 AM UTC 24
Finished Oct 12 12:52:57 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714392147 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2714392147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.337252786
Short name T43
Test name
Test status
Simulation time 39942040 ps
CPU time 1.12 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337252786 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.337252786
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.2909260371
Short name T40
Test name
Test status
Simulation time 40127998 ps
CPU time 0.92 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909260371 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.2909260371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.2408673203
Short name T36
Test name
Test status
Simulation time 44129816 ps
CPU time 0.82 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408673203 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2408673203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.298650214
Short name T39
Test name
Test status
Simulation time 20033645 ps
CPU time 0.83 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298650214 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.298650214
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.1443481194
Short name T178
Test name
Test status
Simulation time 81297317 ps
CPU time 1.02 seconds
Started Oct 12 12:52:57 AM UTC 24
Finished Oct 12 12:52:59 AM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443481194 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1443481194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.3772196402
Short name T239
Test name
Test status
Simulation time 979947072 ps
CPU time 7.9 seconds
Started Oct 12 12:52:57 AM UTC 24
Finished Oct 12 12:53:06 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772196402 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.3772196402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.2894709082
Short name T38
Test name
Test status
Simulation time 74025688 ps
CPU time 0.96 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894709082 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.2894709082
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.852944013
Short name T37
Test name
Test status
Simulation time 19189074 ps
CPU time 0.83 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852944013 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.852944013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.976103221
Short name T41
Test name
Test status
Simulation time 62095340 ps
CPU time 1.12 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976103221 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_ctrl_intersig_mubi.976103221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.1975149193
Short name T179
Test name
Test status
Simulation time 13355810 ps
CPU time 0.73 seconds
Started Oct 12 12:52:59 AM UTC 24
Finished Oct 12 12:53:00 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975149193 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1975149193
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.4079834175
Short name T171
Test name
Test status
Simulation time 1230888562 ps
CPU time 6.93 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 211728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079834175 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.4079834175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.366290221
Short name T72
Test name
Test status
Simulation time 32731692 ps
CPU time 0.96 seconds
Started Oct 12 12:52:57 AM UTC 24
Finished Oct 12 12:52:59 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366290221 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.366290221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.3416146968
Short name T385
Test name
Test status
Simulation time 5665571976 ps
CPU time 43.01 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:45 AM UTC 24
Peak memory 211840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416146968 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.3416146968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.1798309574
Short name T57
Test name
Test status
Simulation time 1715520492 ps
CPU time 29.09 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:30 AM UTC 24
Peak memory 221412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798309574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.1798309574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.666554958
Short name T180
Test name
Test status
Simulation time 87198689 ps
CPU time 1.09 seconds
Started Oct 12 12:52:59 AM UTC 24
Finished Oct 12 12:53:01 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666554958 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.666554958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.1908092232
Short name T238
Test name
Test status
Simulation time 51619971 ps
CPU time 1.1 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:04 AM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908092232 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.1908092232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3984925059
Short name T93
Test name
Test status
Simulation time 48400206 ps
CPU time 1.02 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:04 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984925059 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.3984925059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.4146253661
Short name T42
Test name
Test status
Simulation time 31606343 ps
CPU time 0.77 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146253661 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.4146253661
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.2023625654
Short name T235
Test name
Test status
Simulation time 24807523 ps
CPU time 1.13 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:04 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023625654 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.2023625654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.250219696
Short name T228
Test name
Test status
Simulation time 59779226 ps
CPU time 1.08 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250219696 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.250219696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.2492326622
Short name T13
Test name
Test status
Simulation time 1035561689 ps
CPU time 9.28 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:11 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492326622 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.2492326622
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.3454490065
Short name T103
Test name
Test status
Simulation time 1280953241 ps
CPU time 6 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454490065 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.3454490065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.902807943
Short name T230
Test name
Test status
Simulation time 84715089 ps
CPU time 1.16 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:03 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902807943 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.902807943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.820859828
Short name T232
Test name
Test status
Simulation time 15844400 ps
CPU time 0.83 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:04 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820859828 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.820859828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3883773626
Short name T234
Test name
Test status
Simulation time 25804408 ps
CPU time 1 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:04 AM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883773626
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.3883773626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.3554082128
Short name T229
Test name
Test status
Simulation time 48401316 ps
CPU time 1.12 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:03 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554082128 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3554082128
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.4157904886
Short name T244
Test name
Test status
Simulation time 692781535 ps
CPU time 3.75 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157904886 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.4157904886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.3670770193
Short name T164
Test name
Test status
Simulation time 82237401 ps
CPU time 1.17 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:02 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670770193 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3670770193
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.2646429114
Short name T34
Test name
Test status
Simulation time 2551980555 ps
CPU time 14.84 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 212056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646429114 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.2646429114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.1152759163
Short name T231
Test name
Test status
Simulation time 270218031 ps
CPU time 1.64 seconds
Started Oct 12 12:53:00 AM UTC 24
Finished Oct 12 12:53:03 AM UTC 24
Peak memory 211608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152759163 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1152759163
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.3971814510
Short name T247
Test name
Test status
Simulation time 17008148 ps
CPU time 0.92 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 209164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971814510 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.3971814510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.253302331
Short name T94
Test name
Test status
Simulation time 30218422 ps
CPU time 0.91 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253302331 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.253302331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.3421980532
Short name T201
Test name
Test status
Simulation time 34410679 ps
CPU time 0.76 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:06 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421980532 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.3421980532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.407373748
Short name T208
Test name
Test status
Simulation time 34900924 ps
CPU time 0.87 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407373748 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.407373748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.1651296664
Short name T237
Test name
Test status
Simulation time 70870973 ps
CPU time 1.01 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:04 AM UTC 24
Peak memory 211572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651296664 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1651296664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.1467465842
Short name T33
Test name
Test status
Simulation time 1642184789 ps
CPU time 13.99 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:17 AM UTC 24
Peak memory 211488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467465842 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1467465842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.1225713834
Short name T297
Test name
Test status
Simulation time 1934953060 ps
CPU time 14.97 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:18 AM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225713834 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.1225713834
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.3918509646
Short name T248
Test name
Test status
Simulation time 79287618 ps
CPU time 1.4 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918509646 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.3918509646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.112016979
Short name T246
Test name
Test status
Simulation time 37529817 ps
CPU time 1.07 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112016979 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.112016979
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.458720300
Short name T245
Test name
Test status
Simulation time 44198232 ps
CPU time 1.02 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458720300 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.458720300
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.3273032781
Short name T240
Test name
Test status
Simulation time 40513142 ps
CPU time 0.81 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:06 AM UTC 24
Peak memory 211644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273032781 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3273032781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.2076160090
Short name T172
Test name
Test status
Simulation time 698714214 ps
CPU time 3.56 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:09 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076160090 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2076160090
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.2732412654
Short name T236
Test name
Test status
Simulation time 28013183 ps
CPU time 0.96 seconds
Started Oct 12 12:53:02 AM UTC 24
Finished Oct 12 12:53:04 AM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732412654 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2732412654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.1180009874
Short name T321
Test name
Test status
Simulation time 2764224122 ps
CPU time 19.38 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:26 AM UTC 24
Peak memory 211784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180009874 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.1180009874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.445366108
Short name T465
Test name
Test status
Simulation time 17167459200 ps
CPU time 79.31 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:54:26 AM UTC 24
Peak memory 228716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445366108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.445366108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.2707803780
Short name T241
Test name
Test status
Simulation time 13894424 ps
CPU time 0.87 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:06 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707803780 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2707803780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.3796626841
Short name T257
Test name
Test status
Simulation time 15591002 ps
CPU time 0.88 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:10 AM UTC 24
Peak memory 211496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796626841 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.3796626841
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3099554048
Short name T253
Test name
Test status
Simulation time 59213106 ps
CPU time 1.15 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099554048 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.3099554048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.93588235
Short name T202
Test name
Test status
Simulation time 112624123 ps
CPU time 1.18 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93588235 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.93588235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.1942487757
Short name T251
Test name
Test status
Simulation time 25076545 ps
CPU time 0.83 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942487757 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.1942487757
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.99910530
Short name T249
Test name
Test status
Simulation time 16835207 ps
CPU time 1.09 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99910530 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.99910530
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.1519152254
Short name T14
Test name
Test status
Simulation time 996783984 ps
CPU time 5.14 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:11 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519152254 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1519152254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.1012419201
Short name T272
Test name
Test status
Simulation time 1597084307 ps
CPU time 6.71 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:13 AM UTC 24
Peak memory 211876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012419201 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.1012419201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.3038392469
Short name T252
Test name
Test status
Simulation time 30227169 ps
CPU time 1.08 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 211768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038392469 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.3038392469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.3521521875
Short name T254
Test name
Test status
Simulation time 66729985 ps
CPU time 1.12 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521521875
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.3521521875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.2700546702
Short name T205
Test name
Test status
Simulation time 79881038 ps
CPU time 1.11 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700546702
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.2700546702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.178692993
Short name T250
Test name
Test status
Simulation time 36320304 ps
CPU time 1.11 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:07 AM UTC 24
Peak memory 209160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178692993 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.178692993
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.1525999561
Short name T269
Test name
Test status
Simulation time 733944286 ps
CPU time 3.13 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:12 AM UTC 24
Peak memory 211728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525999561 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1525999561
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.3400380170
Short name T157
Test name
Test status
Simulation time 73280562 ps
CPU time 1.56 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400380170 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.3400380170
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.149226383
Short name T32
Test name
Test status
Simulation time 1419270130 ps
CPU time 5.74 seconds
Started Oct 12 12:53:08 AM UTC 24
Finished Oct 12 12:53:15 AM UTC 24
Peak memory 211780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149226383 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.149226383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.2780005490
Short name T255
Test name
Test status
Simulation time 134089846 ps
CPU time 1.75 seconds
Started Oct 12 12:53:05 AM UTC 24
Finished Oct 12 12:53:08 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780005490 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2780005490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/9.clkmgr_trans/latest
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