Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T27
0	1	Covered	T6,T18,T39
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T50
1	0	Covered	T27,T19,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	184419203	7479	0	0
GateOpen_A	184419203	12996	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184419203	7479	0	0
T4	40554	4	0	0
T5	36011	0	0	0
T6	4355	28	0	0
T18	0	9	0	0
T19	0	9	0	0
T27	4406	5	0	0
T28	4725	0	0	0
T29	6369	0	0	0
T30	26001	0	0	0
T31	8338	0	0	0
T32	12573	0	0	0
T33	32406	0	0	0
T38	0	27	0	0
T39	0	4	0	0
T50	0	4	0	0
T70	0	4	0	0
T93	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184419203	12996	0	0
T1	0	4	0	0
T2	0	24	0	0
T4	40554	8	0	0
T5	36011	0	0	0
T6	4355	28	0	0
T27	4406	9	0	0
T28	4725	4	0	0
T29	6369	4	0	0
T30	26001	4	0	0
T31	8338	0	0	0
T32	12573	0	0	0
T33	32406	4	0	0
T50	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T27
0	1	Covered	T6,T18,T39
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T50
1	0	Covered	T27,T19,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	19922870	1748	0	0
GateOpen_A	19922870	3122	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922870	1748	0	0
T4	4488	1	0	0
T5	4344	0	0	0
T6	462	8	0	0
T18	0	2	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	503	0	0	0
T29	695	0	0	0
T30	3114	0	0	0
T31	923	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T39	0	1	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922870	3122	0	0
T1	0	1	0	0
T2	0	6	0	0
T4	4488	2	0	0
T5	4344	0	0	0
T6	462	8	0	0
T27	478	2	0	0
T28	503	1	0	0
T29	695	1	0	0
T30	3114	1	0	0
T31	923	0	0	0
T32	1509	0	0	0
T33	3891	1	0	0
T50	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T27
0	1	Covered	T6,T18,T39
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T50
1	0	Covered	T27,T19,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	39846176	1925	0	0
GateOpen_A	39846176	3299	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39846176	1925	0	0
T4	8976	1	0	0
T5	8690	0	0	0
T6	923	6	0	0
T18	0	2	0	0
T19	0	2	0	0
T27	956	1	0	0
T28	1005	0	0	0
T29	1389	0	0	0
T30	6231	0	0	0
T31	1846	0	0	0
T32	3019	0	0	0
T33	7785	0	0	0
T38	0	7	0	0
T39	0	1	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39846176	3299	0	0
T1	0	1	0	0
T2	0	6	0	0
T4	8976	2	0	0
T5	8690	0	0	0
T6	923	6	0	0
T27	956	2	0	0
T28	1005	1	0	0
T29	1389	1	0	0
T30	6231	1	0	0
T31	1846	0	0	0
T32	3019	0	0	0
T33	7785	1	0	0
T50	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T27
0	1	Covered	T6,T18,T39
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T50
1	0	Covered	T27,T19,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	81234481	1889	0	0
GateOpen_A	81234481	3273	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81234481	1889	0	0
T4	18060	1	0	0
T5	15318	0	0	0
T6	1980	6	0	0
T18	0	2	0	0
T19	0	2	0	0
T27	1965	1	0	0
T28	2145	0	0	0
T29	2857	0	0	0
T30	11104	0	0	0
T31	3713	0	0	0
T32	5363	0	0	0
T33	13820	0	0	0
T38	0	7	0	0
T39	0	1	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81234481	3273	0	0
T1	0	1	0	0
T2	0	6	0	0
T4	18060	2	0	0
T5	15318	0	0	0
T6	1980	6	0	0
T27	1965	2	0	0
T28	2145	1	0	0
T29	2857	1	0	0
T30	11104	1	0	0
T31	3713	0	0	0
T32	5363	0	0	0
T33	13820	1	0	0
T50	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T27
0	1	Covered	T6,T18,T39
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T50
1	0	Covered	T27,T19,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	43415676	1917	0	0
GateOpen_A	43415676	3302	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43415676	1917	0	0
T4	9030	1	0	0
T5	7659	0	0	0
T6	990	8	0	0
T18	0	3	0	0
T19	0	3	0	0
T27	1007	2	0	0
T28	1072	0	0	0
T29	1428	0	0	0
T30	5552	0	0	0
T31	1856	0	0	0
T32	2682	0	0	0
T33	6910	0	0	0
T38	0	6	0	0
T39	0	1	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43415676	3302	0	0
T1	0	1	0	0
T2	0	6	0	0
T4	9030	2	0	0
T5	7659	0	0	0
T6	990	8	0	0
T27	1007	3	0	0
T28	1072	1	0	0
T29	1428	1	0	0
T30	5552	1	0	0
T31	1856	0	0	0
T32	2682	0	0	0
T33	6910	1	0	0
T50	0	2	0	0