Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	186936745	30999	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186936745	30999	0	0
T3	142655	39	0	0
T7	0	36	0	0
T8	0	188	0	0
T10	0	203	0	0
T11	0	126	0	0
T12	0	435	0	0
T13	0	412	0	0
T14	0	440	0	0
T15	0	396	0	0
T16	0	139	0	0
T17	10885	0	0	0
T18	4585	0	0	0
T19	6880	0	0	0
T20	14805	0	0	0
T21	4770	0	0	0
T22	48085	0	0	0
T23	10090	0	0	0
T24	6775	0	0	0
T25	5505	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	37387349	4608	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	4608	0	0
T3	28531	6	0	0
T7	0	6	0	0
T8	0	28	0	0
T10	0	26	0	0
T11	0	20	0	0
T12	0	55	0	0
T13	0	61	0	0
T14	0	65	0	0
T15	0	59	0	0
T16	0	19	0	0
T17	2177	0	0	0
T18	917	0	0	0
T19	1376	0	0	0
T20	2961	0	0	0
T21	954	0	0	0
T22	9617	0	0	0
T23	2018	0	0	0
T24	1355	0	0	0
T25	1101	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	37387349	4539	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	4539	0	0
T3	28531	6	0	0
T7	0	6	0	0
T8	0	23	0	0
T10	0	25	0	0
T11	0	20	0	0
T12	0	63	0	0
T13	0	52	0	0
T14	0	56	0	0
T15	0	48	0	0
T16	0	19	0	0
T17	2177	0	0	0
T18	917	0	0	0
T19	1376	0	0	0
T20	2961	0	0	0
T21	954	0	0	0
T22	9617	0	0	0
T23	2018	0	0	0
T24	1355	0	0	0
T25	1101	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	37387349	6205	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	6205	0	0
T3	28531	8	0	0
T7	0	7	0	0
T8	0	36	0	0
T10	0	42	0	0
T11	0	25	0	0
T12	0	88	0	0
T13	0	81	0	0
T14	0	85	0	0
T15	0	78	0	0
T16	0	28	0	0
T17	2177	0	0	0
T18	917	0	0	0
T19	1376	0	0	0
T20	2961	0	0	0
T21	954	0	0	0
T22	9617	0	0	0
T23	2018	0	0	0
T24	1355	0	0	0
T25	1101	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	37387349	6218	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	6218	0	0
T3	28531	8	0	0
T7	0	7	0	0
T8	0	39	0	0
T10	0	39	0	0
T11	0	26	0	0
T12	0	86	0	0
T13	0	84	0	0
T14	0	87	0	0
T15	0	83	0	0
T16	0	27	0	0
T17	2177	0	0	0
T18	917	0	0	0
T19	1376	0	0	0
T20	2961	0	0	0
T21	954	0	0	0
T22	9617	0	0	0
T23	2018	0	0	0
T24	1355	0	0	0
T25	1101	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	37387349	9429	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	9429	0	0
T3	28531	11	0	0
T7	0	10	0	0
T8	0	62	0	0
T10	0	71	0	0
T11	0	35	0	0
T12	0	143	0	0
T13	0	134	0	0
T14	0	147	0	0
T15	0	128	0	0
T16	0	46	0	0
T17	2177	0	0	0
T18	917	0	0	0
T19	1376	0	0	0
T20	2961	0	0	0
T21	954	0	0	0
T22	9617	0	0	0
T23	2018	0	0	0
T24	1355	0	0	0
T25	1101	0	0	0