Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T22,T37

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	37387349	35180470	0	0
AllClkBypReqTrue_A	37387349	79983	0	0
IoClkBypReqFalse_A	37387349	35128831	0	2364
IoClkBypReqTrue_A	37387349	127496	0	0
LcClkBypAckFalse_A	37387349	35187438	0	0
LcClkBypAckTrue_A	37387349	73015	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	35180470	0	0
T4	1317	1303	0	0
T5	1595	1399	0	0
T6	1960	1730	0	0
T27	1050	987	0	0
T28	2233	1948	0	0
T29	2887	2750	0	0
T30	1734	1632	0	0
T31	1236	1136	0	0
T32	1340	1170	0	0
T33	2015	1805	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	79983	0	0
T1	49917	0	0	0
T5	1595	174	0	0
T6	1960	0	0	0
T17	0	256	0	0
T23	0	48	0	0
T24	0	9	0	0
T25	0	131	0	0
T27	1050	0	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	68	0	0
T31	1236	32	0	0
T32	1340	128	0	0
T33	2015	201	0	0
T99	0	78	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	35128831	0	2364
T4	1317	1301	0	3
T5	1595	1268	0	3
T6	1960	1728	0	3
T27	1050	985	0	3
T28	2233	1946	0	3
T29	2887	2748	0	3
T30	1734	1359	0	3
T31	1236	1166	0	3
T32	1340	1149	0	3
T33	2015	1576	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	127496	0	0
T1	49917	0	0	0
T5	1595	303	0	0
T6	1960	0	0	0
T17	0	380	0	0
T23	0	43	0	0
T24	0	186	0	0
T25	0	157	0	0
T27	1050	0	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	339	0	0
T31	1236	0	0	0
T32	1340	147	0	0
T33	2015	428	0	0
T99	0	172	0	0
T100	0	137	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	35187438	0	0
T4	1317	1303	0	0
T5	1595	1408	0	0
T6	1960	1730	0	0
T27	1050	987	0	0
T28	2233	1948	0	0
T29	2887	2750	0	0
T30	1734	1490	0	0
T31	1236	1168	0	0
T32	1340	1224	0	0
T33	2015	1788	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	73015	0	0
T1	49917	0	0	0
T5	1595	165	0	0
T6	1960	0	0	0
T17	0	164	0	0
T24	0	102	0	0
T25	0	68	0	0
T27	1050	0	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	210	0	0
T31	1236	0	0	0
T32	1340	74	0	0
T33	2015	218	0	0
T43	0	26	0	0
T99	0	103	0	0
T100	0	72	0	0