Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	361557936	10044	0	0
TransStop_A	361557936	5232	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361557936	10044	0	0
T4	75248	4	0	0
T5	63824	0	0	0
T6	8252	0	0	0
T20	0	31	0	0
T21	0	3	0	0
T27	8112	0	0	0
T28	8936	27	0	0
T29	11904	26	0	0
T30	46268	0	0	0
T31	15468	0	0	0
T32	22344	0	0	0
T33	57588	0	0	0
T40	0	6	0	0
T41	0	6	0	0
T50	0	4	0	0
T70	0	4	0	0
T93	0	4	0	0
T123	0	19	0	0
T124	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361557936	5232	0	0
T4	75248	4	0	0
T5	63824	0	0	0
T6	8252	0	0	0
T20	0	19	0	0
T21	0	3	0	0
T27	8112	0	0	0
T28	8936	18	0	0
T29	11904	9	0	0
T30	46268	0	0	0
T31	15468	0	0	0
T32	22344	0	0	0
T33	57588	0	0	0
T40	0	6	0	0
T41	0	1	0	0
T50	0	4	0	0
T70	0	4	0	0
T93	0	4	0	0
T123	0	18	0	0
T124	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	90389484	2501	0	0
TransStop_A	90389484	1312	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	2501	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	11	0	0
T21	0	1	0	0
T27	2028	0	0	0
T28	2234	6	0	0
T29	2976	5	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	1312	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	2028	0	0	0
T28	2234	4	0	0
T29	2976	3	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T40	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0
T123	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	90389484	2470	0	0
TransStop_A	90389484	1279	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	2470	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	2028	0	0	0
T28	2234	8	0	0
T29	2976	7	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0
T123	0	8	0	0
T124	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	1279	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T27	2028	0	0	0
T28	2234	5	0	0
T29	2976	1	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0
T123	0	5	0	0
T124	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	90389484	2585	0	0
TransStop_A	90389484	1373	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	2585	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	6	0	0
T27	2028	0	0	0
T28	2234	4	0	0
T29	2976	8	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0
T123	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	1373	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	4	0	0
T27	2028	0	0	0
T28	2234	3	0	0
T29	2976	2	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0
T123	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	90389484	2488	0	0
TransStop_A	90389484	1268	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	2488	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	2028	0	0	0
T28	2234	9	0	0
T29	2976	6	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389484	1268	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2063	0	0	0
T20	0	4	0	0
T21	0	1	0	0
T27	2028	0	0	0
T28	2234	6	0	0
T29	2976	3	0	0
T30	11567	0	0	0
T31	3867	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T40	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0