Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	38348859	551410	0	0
clk_enables_rd_A	38348859	7872	0	0
clk_hints_rd_A	38348859	7593	0	0
extclk_ctrl_rd_A	38348859	10319	0	0
extclk_ctrl_regwen_rd_A	38348859	6632	0	0
jitter_enable_rd_A	38348859	12068	0	0
jitter_regwen_rd_A	38348859	6154	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38348859	551410	0	0
T10	144961	6670	0	0
T11	55768	0	0	0
T35	19055	0	0	0
T52	0	5661	0	0
T53	0	6576	0	0
T54	0	6311	0	0
T55	0	10003	0	0
T56	0	3124	0	0
T57	0	13580	0	0
T58	0	3933	0	0
T59	0	1073	0	0
T60	0	18850	0	0
T61	1001	0	0	0
T62	2944	0	0	0
T63	1716	0	0	0
T64	2269	0	0	0
T65	2064	0	0	0
T66	32887	0	0	0
T67	1118	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38348859	7872	0	0
T12	504439	12	0	0
T52	185308	308	0	0
T53	0	287	0	0
T55	0	367	0	0
T59	0	53	0	0
T142	0	9	0	0
T143	0	6	0	0
T144	0	7	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	1593	0	0	0
T148	2241	0	0	0
T149	769	0	0	0
T150	2054	0	0	0
T151	3327	0	0	0
T152	1013	0	0	0
T153	1686	0	0	0
T154	2396	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38348859	7593	0	0
T12	504439	12	0	0
T52	185308	246	0	0
T53	0	200	0	0
T55	0	455	0	0
T59	0	80	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	1	0	0
T146	0	7	0	0
T147	1593	0	0	0
T148	2241	0	0	0
T149	769	0	0	0
T150	2054	0	0	0
T151	3327	0	0	0
T152	1013	0	0	0
T153	1686	0	0	0
T154	2396	0	0	0
T155	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38348859	10319	0	0
T9	11469	25	0	0
T26	105632	110	0	0
T44	2405	60	0	0
T45	46047	0	0	0
T46	25434	0	0	0
T62	0	69	0	0
T68	1731	18	0	0
T69	902	0	0	0
T70	1642	0	0	0
T71	1515	0	0	0
T72	16505	0	0	0
T156	0	16	0	0
T157	0	25	0	0
T158	0	63	0	0
T159	0	54	0	0
T160	0	41	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38348859	6632	0	0
T9	11469	17	0	0
T26	105632	65	0	0
T52	0	250	0	0
T53	0	245	0	0
T55	0	418	0	0
T59	0	45	0	0
T69	902	0	0	0
T70	1642	0	0	0
T71	1515	0	0	0
T72	16505	0	0	0
T122	0	42	0	0
T123	2725	0	0	0
T124	3182	0	0	0
T161	0	33	0	0
T162	0	1	0	0
T163	0	195	0	0
T164	1173	0	0	0
T165	1600	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38348859	12068	0	0
T12	0	190	0	0
T52	0	358	0	0
T53	0	399	0	0
T142	0	84	0	0
T143	0	84	0	0
T144	0	124	0	0
T145	0	120	0	0
T155	0	82	0	0
T166	2040	53	0	0
T167	0	53	0	0
T168	1178	0	0	0
T169	64735	0	0	0
T170	1897	0	0	0
T171	1964	0	0	0
T172	1682	0	0	0
T173	2156	0	0	0
T174	12197	0	0	0
T175	1993	0	0	0
T176	93228	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38348859	6154	0	0
T12	504439	0	0	0
T52	185308	269	0	0
T53	0	258	0	0
T55	0	402	0	0
T59	0	81	0	0
T147	1593	0	0	0
T148	2241	0	0	0
T149	769	0	0	0
T150	2054	0	0	0
T151	3327	0	0	0
T152	1013	0	0	0
T153	1686	0	0	0
T154	2396	0	0	0
T163	0	176	0	0
T177	0	74	0	0
T178	0	223	0	0
T179	0	292	0	0
T180	0	161	0	0
T181	0	295	0	0