Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72003478

1

T4

2608

T5

2542

T6

3462

auto[1]

254992

1

T5

606

T30

678

T32

294

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72000810

1

T4

2608

T5

2724

T6

3462

auto[1]

257660

1

T5

424

T30

574

T31

26

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71937748

1

T4

2608

T5

2666

T6

3462

auto[1]

320722

1

T5

482

T30

678

T31

72

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70540998

1

T4

2608

T5

744

T6

3462

auto[1]

1717472

1

T5

2404

T30

296

T31

2180

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51731948

1

T4

2608

T5

1520

T6

472

auto[1]

20526522

1

T5

1628

T6

2990

T28

2506

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50196760

1

T4

2608

T5

370

T6

472

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20120764

1

T5

188

T6

2990

T28

2506

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

18038

1

T5

40

T30

278

T33

30

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4514

1

T5

12

T33

32

T17

28

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1159824

1

T5

644

T31

2116

T32

490

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

332702

1

T5

1202

T30

160

T33

256

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

31140

1

T5

88

T32

26

T33

30

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7606

1

T5

32

T33

12

T17

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

28322

1

T30

24

T17

22

T23

26

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1046

1

T33

10

T188

2

T189

18

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8796

1

T17

56

T68

58

T71

52

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2002

1

T188

42

T86

50

T15

64

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

7036

1

T5

16

T32

30

T33

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2106

1

T5

10

T33

10

T17

12

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13282

1

T32

148

T33

60

T17

62

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3810

1

T5

64

T33

118

T189

66

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38484

1

T5

6

T30

68

T33

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2356

1

T33

22

T23

48

T159

20

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

18142

1

T5

50

T30

60

T33

38

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5232

1

T33

40

T159

86

T64

130

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

18102

1

T5

10

T31

46

T32

68

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4964

1

T5

2

T33

12

T17

34

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33270

1

T5

40

T32

74

T33

102

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8912

1

T5

40

T17

136

T25

84

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53082

1

T5

16

T30

142

T32

42

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3926

1

T5

10

T31

8

T33

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

31372

1

T30

272

T33

110

T17

76

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8162

1

T5

52

T33

44

T17

62

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27712

1

T5

52

T31

18

T32

68

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6292

1

T5

16

T30

68

T33

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

48586

1

T5

188

T32

46

T33

198

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12128

1

T30

68

T33

42

T17

78