Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 338370206 1 T4 2326 T5 2164 T6 2754
auto[1] 452664 1 T5 246 T30 318 T31 56


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 338400940 1 T4 2326 T5 2286 T6 2754
auto[1] 421930 1 T5 124 T30 310 T31 62


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 338321810 1 T4 2326 T5 2222 T6 2754
auto[1] 501060 1 T5 188 T30 396 T31 70


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 316979572 1 T4 2326 T5 128 T6 2754
auto[1] 21843298 1 T5 2282 T31 2200 T33 2788


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 189849712 1 T4 2288 T5 2410 T6 92
auto[1] 148973158 1 T4 38 T6 2662 T29 898


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cp   csr_low_speed_cp   hw_debug_en_cp   byp_req_cp   scanmode_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] auto[0] auto[0] auto[0] 173555104 1 T4 2288 T5 120 T6 92
auto[0] auto[0] auto[0] auto[0] auto[1] 143088030 1 T4 38 T6 2662 T29 898
auto[0] auto[0] auto[0] auto[1] auto[0] 34248 1 T30 10 T34 2 T56 8
auto[0] auto[0] auto[0] auto[1] auto[1] 9316 1 T19 32 T62 22 T168 30
auto[0] auto[0] auto[1] auto[0] auto[0] 15690896 1 T5 2010 T31 2130 T33 2510
auto[0] auto[0] auto[1] auto[0] auto[1] 5756960 1 T33 112 T34 2226 T104 60
auto[0] auto[0] auto[1] auto[1] auto[0] 57074 1 T5 92 T34 98 T104 32
auto[0] auto[0] auto[1] auto[1] auto[1] 14602 1 T104 10 T19 50 T23 94
auto[0] auto[1] auto[0] auto[0] auto[0] 56464 1 T34 2 T56 20 T57 8
auto[0] auto[1] auto[0] auto[0] auto[1] 1556 1 T19 12 T13 8 T114 6
auto[0] auto[1] auto[0] auto[1] auto[0] 12408 1 T34 52 T62 64 T168 134
auto[0] auto[1] auto[0] auto[1] auto[1] 3630 1 T19 80 T114 42 T202 62
auto[0] auto[1] auto[1] auto[0] auto[0] 10972 1 T33 22 T34 8 T57 8
auto[0] auto[1] auto[1] auto[0] auto[1] 3458 1 T56 42 T57 8 T13 36
auto[0] auto[1] auto[1] auto[1] auto[0] 21284 1 T203 66 T168 224 T13 166
auto[0] auto[1] auto[1] auto[1] auto[1] 5808 1 T13 150 T14 64 T204 42
auto[1] auto[0] auto[0] auto[0] auto[0] 33558 1 T5 8 T30 20 T33 38
auto[1] auto[0] auto[0] auto[0] auto[1] 4216 1 T30 2 T104 10 T62 6
auto[1] auto[0] auto[0] auto[1] auto[0] 35174 1 T56 42 T59 150 T61 58
auto[1] auto[0] auto[0] auto[1] auto[1] 8254 1 T30 64 T62 54 T45 50
auto[1] auto[0] auto[1] auto[0] auto[0] 30796 1 T5 2 T31 8 T33 80
auto[1] auto[0] auto[1] auto[0] auto[1] 7882 1 T33 8 T104 2 T57 12
auto[1] auto[0] auto[1] auto[1] auto[0] 59622 1 T5 54 T34 166 T19 66
auto[1] auto[0] auto[1] auto[1] auto[1] 15208 1 T104 50 T19 64 T63 66
auto[1] auto[1] auto[0] auto[0] auto[0] 63876 1 T30 40 T33 8 T34 20
auto[1] auto[1] auto[0] auto[0] auto[1] 6986 1 T30 26 T33 26 T34 8
auto[1] auto[1] auto[0] auto[1] auto[0] 52618 1 T30 202 T56 116 T58 62
auto[1] auto[1] auto[0] auto[1] auto[1] 14134 1 T30 42 T19 88 T168 84
auto[1] auto[1] auto[1] auto[0] auto[0] 48570 1 T5 24 T31 6 T33 32
auto[1] auto[1] auto[1] auto[0] auto[1] 10882 1 T33 24 T34 38 T19 10
auto[1] auto[1] auto[1] auto[1] auto[0] 87048 1 T5 100 T31 56 T34 102
auto[1] auto[1] auto[1] auto[1] auto[1] 22236 1 T34 36 T19 66 T61 60