Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total tests in report: 1010
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
51.84 51.84 68.15 68.15 43.60 43.60 80.60 80.60 0.00 0.00 73.45 73.45 71.45 71.45 25.64 25.64 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.260141068
84.11 32.27 94.86 26.71 76.18 32.58 82.53 1.93 100.00 100.00 94.47 21.02 84.52 13.07 56.24 30.60 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.3510443877
88.91 4.79 95.92 1.06 82.92 6.74 94.93 12.40 100.00 0.00 96.07 1.60 85.51 0.99 67.01 10.77 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.3571871232
91.02 2.11 96.41 0.49 85.02 2.10 95.09 0.16 100.00 0.00 96.13 0.05 85.51 0.00 78.97 11.97 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.1692212339
92.61 1.60 97.65 1.24 86.76 1.74 95.73 0.64 100.00 0.00 97.47 1.34 87.78 2.27 82.91 3.93 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.3561078348
93.97 1.36 97.68 0.02 88.25 1.49 96.38 0.64 100.00 0.00 97.52 0.05 88.92 1.14 89.06 6.15 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.3262355730
95.32 1.35 98.08 0.40 92.25 4.00 96.86 0.48 100.00 0.00 97.62 0.10 91.48 2.56 90.94 1.88 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3772827481
96.09 0.77 98.38 0.31 92.49 0.24 98.63 1.77 100.00 0.00 98.09 0.46 92.19 0.71 92.82 1.88 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.987578347
96.85 0.76 98.50 0.12 92.98 0.48 99.11 0.48 100.00 0.00 98.09 0.00 96.45 4.26 92.82 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.3238152432
97.46 0.61 98.50 0.00 93.10 0.12 99.68 0.56 100.00 0.00 98.09 0.00 96.45 0.00 96.41 3.59 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.1654407331
97.71 0.25 98.97 0.47 93.78 0.69 99.68 0.00 100.00 0.00 98.71 0.62 96.45 0.00 96.41 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.430009267
97.93 0.22 98.97 0.00 93.94 0.16 99.68 0.00 100.00 0.00 98.71 0.00 96.45 0.00 97.78 1.37 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.239835774
98.10 0.17 98.99 0.02 94.67 0.73 99.68 0.00 100.00 0.00 98.71 0.00 96.73 0.28 97.95 0.17 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.582673974
98.20 0.09 99.11 0.12 94.87 0.20 100.00 0.32 100.00 0.00 98.71 0.00 96.73 0.00 97.95 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.227812304
98.24 0.05 99.11 0.00 94.87 0.00 100.00 0.00 100.00 0.00 98.71 0.00 96.73 0.00 98.29 0.34 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2866060893
98.29 0.04 99.15 0.05 95.03 0.16 100.00 0.00 100.00 0.00 98.81 0.10 96.73 0.00 98.29 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.2063396625
98.33 0.04 99.15 0.00 95.20 0.16 100.00 0.00 100.00 0.00 98.81 0.00 96.88 0.14 98.29 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.879341447
98.37 0.04 99.15 0.00 95.28 0.08 100.00 0.00 100.00 0.00 98.81 0.00 96.88 0.00 98.46 0.17 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.4031718209
98.39 0.02 99.15 0.00 95.28 0.00 100.00 0.00 100.00 0.00 98.81 0.00 96.88 0.00 98.63 0.17 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.107031486
98.42 0.02 99.15 0.00 95.28 0.00 100.00 0.00 100.00 0.00 98.81 0.00 96.88 0.00 98.80 0.17 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.3472937462
98.44 0.02 99.15 0.00 95.44 0.16 100.00 0.00 100.00 0.00 98.81 0.00 96.88 0.00 98.80 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2439721728
98.46 0.02 99.15 0.00 95.44 0.00 100.00 0.00 100.00 0.00 98.81 0.00 97.02 0.14 98.80 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3907405656
98.48 0.02 99.15 0.00 95.56 0.12 100.00 0.00 100.00 0.00 98.81 0.00 97.02 0.00 98.80 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2137605247
98.48 0.01 99.15 0.00 95.60 0.04 100.00 0.00 100.00 0.00 98.81 0.00 97.02 0.00 98.80 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3998694327
98.49 0.01 99.15 0.00 95.64 0.04 100.00 0.00 100.00 0.00 98.81 0.00 97.02 0.00 98.80 0.00 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3747007634

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.484724460
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2627611125
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.4208681592
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2787329818
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.3755302611
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.3554159753
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3224375675
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.787562386
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.27453560
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1869780782
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2513130169
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1387712075
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.607252302
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1136577562
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.456300270
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.813807062
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3171664270
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.327073871
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.516129293
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1645099304
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2302421799
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.3698304980
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.2003736220
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2299681393
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.33542694
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1326562526
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.1181286829
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3989867039
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.1998226656
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.2936609199
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1712721631
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4269151594
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2278763772
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.3227295321
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2789554945
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.805318925
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.751646706
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.3252917936
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1486587161
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3892562135
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3190571442
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.885230584
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.855256795
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.928557344
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.933185716
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.2527463512
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2066862616
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2318444066
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1981356465
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.2351483898
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3543395905
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3139554536
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.41120175
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.1499844157
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.987772073
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1698751080
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4048510055
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.710190826
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3357385707
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.95428730
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.635095932
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.3226002492
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.738141679
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2019409411
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.240826140
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.1733153542
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.747896411
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1837304838
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.1123956243
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.1276472991
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2073577057
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2079641715
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.729160410
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3688724163
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.583169713
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.2086803405
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.293300012
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.442259291
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3218493757
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1342549198
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.2436550287
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.4043176644
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.858602080
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.3243978078
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.18759412
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3948255319
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.280805156
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3584778104
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2866464821
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.4113768729
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.3253642176
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.3558225209
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2776825780
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1190215293
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3884018556
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.3863046523
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2045637396
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2744441637
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3265155945
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.4039956680
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3771133706
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.4080021858
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.2407197257
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.65294621
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2854188303
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1925786532
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/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.4076813859
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.121693833
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.531720434
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.3510086553
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.2684650466
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.1209430929
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.1053439524
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2381444207
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.825220966
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.3635582194
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.2358565884
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.913450827
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.3852095272
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.4034333387
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.2355109712



Total test records in report: 1010
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.3171486846 Feb 09 08:16:09 AM UTC 25 Feb 09 08:16:11 AM UTC 25 17152148 ps
T5 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.3431089618 Feb 09 08:16:09 AM UTC 25 Feb 09 08:16:12 AM UTC 25 82050616 ps
T6 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.430009267 Feb 09 08:16:10 AM UTC 25 Feb 09 08:16:12 AM UTC 25 14622230 ps
T28 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.3238152432 Feb 09 08:16:10 AM UTC 25 Feb 09 08:16:12 AM UTC 25 13774458 ps
T29 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.725489414 Feb 09 08:16:10 AM UTC 25 Feb 09 08:16:12 AM UTC 25 62610371 ps
T30 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2971784146 Feb 09 08:16:11 AM UTC 25 Feb 09 08:16:14 AM UTC 25 30311295 ps
T31 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.260141068 Feb 09 08:16:11 AM UTC 25 Feb 09 08:16:14 AM UTC 25 13425035 ps
T32 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.3561078348 Feb 09 08:16:11 AM UTC 25 Feb 09 08:16:14 AM UTC 25 22460195 ps
T33 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2866060893 Feb 09 08:16:11 AM UTC 25 Feb 09 08:16:14 AM UTC 25 70308433 ps
T34 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.1183323880 Feb 09 08:16:12 AM UTC 25 Feb 09 08:16:15 AM UTC 25 21318830 ps
T69 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.227812304 Feb 09 08:16:14 AM UTC 25 Feb 09 08:16:16 AM UTC 25 80647657 ps
T68 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.715465861 Feb 09 08:16:15 AM UTC 25 Feb 09 08:16:17 AM UTC 25 14439240 ps
T104 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.1916830376 Feb 09 08:16:15 AM UTC 25 Feb 09 08:16:17 AM UTC 25 16394744 ps
T1 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.3571871232 Feb 09 08:16:12 AM UTC 25 Feb 09 08:16:18 AM UTC 25 493915025 ps
T51 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.764897134 Feb 09 08:16:16 AM UTC 25 Feb 09 08:16:18 AM UTC 25 17109418 ps
T52 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.3732036377 Feb 09 08:16:17 AM UTC 25 Feb 09 08:16:19 AM UTC 25 22389972 ps
T53 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.3611914082 Feb 09 08:16:18 AM UTC 25 Feb 09 08:16:20 AM UTC 25 12025360 ps
T54 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.3305713584 Feb 09 08:16:18 AM UTC 25 Feb 09 08:16:20 AM UTC 25 20249779 ps
T55 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.987578347 Feb 09 08:16:12 AM UTC 25 Feb 09 08:16:20 AM UTC 25 586731592 ps
T56 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2135980226 Feb 09 08:16:19 AM UTC 25 Feb 09 08:16:22 AM UTC 25 30903083 ps
T57 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1826983368 Feb 09 08:16:19 AM UTC 25 Feb 09 08:16:22 AM UTC 25 61753511 ps
T58 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3907405656 Feb 09 08:16:20 AM UTC 25 Feb 09 08:16:23 AM UTC 25 19011829 ps
T2 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.3297973451 Feb 09 08:16:10 AM UTC 25 Feb 09 08:16:23 AM UTC 25 1534516919 ps
T3 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.1423458037 Feb 09 08:16:15 AM UTC 25 Feb 09 08:16:23 AM UTC 25 1350029520 ps
T19 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.1654407331 Feb 09 08:16:21 AM UTC 25 Feb 09 08:16:24 AM UTC 25 30269995 ps
T20 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.794205438 Feb 09 08:16:21 AM UTC 25 Feb 09 08:16:26 AM UTC 25 153301237 ps
T21 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.3812454709 Feb 09 08:16:24 AM UTC 25 Feb 09 08:16:26 AM UTC 25 48131736 ps
T22 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.440004051 Feb 09 08:16:24 AM UTC 25 Feb 09 08:16:26 AM UTC 25 54842568 ps
T23 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.3094708637 Feb 09 08:16:25 AM UTC 25 Feb 09 08:16:27 AM UTC 25 37159199 ps
T24 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.2637274166 Feb 09 08:16:27 AM UTC 25 Feb 09 08:16:29 AM UTC 25 15203015 ps
T25 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.301740166 Feb 09 08:16:27 AM UTC 25 Feb 09 08:16:29 AM UTC 25 21398050 ps
T26 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.1980773892 Feb 09 08:16:28 AM UTC 25 Feb 09 08:16:30 AM UTC 25 14171993 ps
T11 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.3853561362 Feb 09 08:16:21 AM UTC 25 Feb 09 08:16:31 AM UTC 25 734361828 ps
T9 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.1782338553 Feb 09 08:16:25 AM UTC 25 Feb 09 08:16:31 AM UTC 25 518085318 ps
T40 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.303490718 Feb 09 08:16:27 AM UTC 25 Feb 09 08:16:32 AM UTC 25 395000371 ps
T59 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1567037184 Feb 09 08:16:30 AM UTC 25 Feb 09 08:16:32 AM UTC 25 33083231 ps
T60 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.3903365559 Feb 09 08:16:30 AM UTC 25 Feb 09 08:16:33 AM UTC 25 28893175 ps
T50 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.3635684348 Feb 09 08:16:10 AM UTC 25 Feb 09 08:16:33 AM UTC 25 2061675138 ps
T61 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.167474363 Feb 09 08:16:31 AM UTC 25 Feb 09 08:16:34 AM UTC 25 36353639 ps
T62 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2122989267 Feb 09 08:16:31 AM UTC 25 Feb 09 08:16:34 AM UTC 25 24109615 ps
T63 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.3130642587 Feb 09 08:16:32 AM UTC 25 Feb 09 08:16:35 AM UTC 25 28178101 ps
T64 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.312798757 Feb 09 08:16:35 AM UTC 25 Feb 09 08:16:37 AM UTC 25 14880398 ps
T65 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.783202949 Feb 09 08:16:35 AM UTC 25 Feb 09 08:16:37 AM UTC 25 20834732 ps
T67 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.3887758845 Feb 09 08:16:33 AM UTC 25 Feb 09 08:16:38 AM UTC 25 156577662 ps
T203 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.1611400248 Feb 09 08:16:36 AM UTC 25 Feb 09 08:16:38 AM UTC 25 18829279 ps
T198 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.1205662841 Feb 09 08:16:39 AM UTC 25 Feb 09 08:16:42 AM UTC 25 50253289 ps
T39 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.709504067 Feb 09 08:16:38 AM UTC 25 Feb 09 08:16:42 AM UTC 25 236249148 ps
T43 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.1746342481 Feb 09 08:16:39 AM UTC 25 Feb 09 08:16:43 AM UTC 25 151989196 ps
T27 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.3897916883 Feb 09 08:16:33 AM UTC 25 Feb 09 08:16:43 AM UTC 25 1086710321 ps
T10 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.3510443877 Feb 09 08:16:15 AM UTC 25 Feb 09 08:16:43 AM UTC 25 2482005324 ps
T44 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.118517668 Feb 09 08:16:42 AM UTC 25 Feb 09 08:16:45 AM UTC 25 126800349 ps
T45 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1014210168 Feb 09 08:16:43 AM UTC 25 Feb 09 08:16:46 AM UTC 25 12922990 ps
T46 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.152468096 Feb 09 08:16:44 AM UTC 25 Feb 09 08:16:46 AM UTC 25 33304733 ps
T47 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.1959155684 Feb 09 08:16:43 AM UTC 25 Feb 09 08:16:46 AM UTC 25 65559739 ps
T48 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1586662536 Feb 09 08:16:45 AM UTC 25 Feb 09 08:16:47 AM UTC 25 34788241 ps
T49 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.139831087 Feb 09 08:16:46 AM UTC 25 Feb 09 08:16:48 AM UTC 25 19728038 ps
T77 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.1312245438 Feb 09 08:16:47 AM UTC 25 Feb 09 08:16:51 AM UTC 25 221451964 ps
T205 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.2687611169 Feb 09 08:16:49 AM UTC 25 Feb 09 08:16:51 AM UTC 25 47907397 ps
T167 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.418768081 Feb 09 08:16:47 AM UTC 25 Feb 09 08:16:53 AM UTC 25 459470135 ps
T206 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.604388366 Feb 09 08:16:52 AM UTC 25 Feb 09 08:16:54 AM UTC 25 38160476 ps
T136 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.2295661841 Feb 09 08:16:52 AM UTC 25 Feb 09 08:16:55 AM UTC 25 51049260 ps
T159 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.3562489743 Feb 09 08:16:55 AM UTC 25 Feb 09 08:16:58 AM UTC 25 37567866 ps
T160 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.2581108594 Feb 09 08:16:58 AM UTC 25 Feb 09 08:17:01 AM UTC 25 28516390 ps
T161 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.1119664071 Feb 09 08:17:02 AM UTC 25 Feb 09 08:17:04 AM UTC 25 16339855 ps
T12 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.1682585655 Feb 09 08:16:53 AM UTC 25 Feb 09 08:17:07 AM UTC 25 1327884750 ps
T162 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2587195231 Feb 09 08:17:07 AM UTC 25 Feb 09 08:17:10 AM UTC 25 22364474 ps
T163 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.3058476774 Feb 09 08:17:07 AM UTC 25 Feb 09 08:17:10 AM UTC 25 20221035 ps
T164 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2379144853 Feb 09 08:17:09 AM UTC 25 Feb 09 08:17:11 AM UTC 25 45205952 ps
T66 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.3635383990 Feb 09 08:16:55 AM UTC 25 Feb 09 08:17:13 AM UTC 25 2341348311 ps
T165 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.863549618 Feb 09 08:17:11 AM UTC 25 Feb 09 08:17:13 AM UTC 25 28355196 ps
T168 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.105572452 Feb 09 08:17:11 AM UTC 25 Feb 09 08:17:14 AM UTC 25 99176533 ps
T137 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.3085459389 Feb 09 08:16:38 AM UTC 25 Feb 09 08:17:16 AM UTC 25 2422489144 ps
T105 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.651904842 Feb 09 08:17:12 AM UTC 25 Feb 09 08:17:17 AM UTC 25 382080100 ps
T13 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.1692212339 Feb 09 08:16:23 AM UTC 25 Feb 09 08:17:18 AM UTC 25 9376249050 ps
T207 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.3949763402 Feb 09 08:17:18 AM UTC 25 Feb 09 08:17:20 AM UTC 25 16590479 ps
T208 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.2864573161 Feb 09 08:17:18 AM UTC 25 Feb 09 08:17:20 AM UTC 25 16247204 ps
T209 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.4050247690 Feb 09 08:17:18 AM UTC 25 Feb 09 08:17:21 AM UTC 25 45141673 ps
T76 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.4188818341 Feb 09 08:17:13 AM UTC 25 Feb 09 08:17:22 AM UTC 25 900453296 ps
T210 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.3367583384 Feb 09 08:17:21 AM UTC 25 Feb 09 08:17:24 AM UTC 25 70390424 ps
T211 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.3551350468 Feb 09 08:17:21 AM UTC 25 Feb 09 08:17:24 AM UTC 25 32302594 ps
T14 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.1031676430 Feb 09 08:16:48 AM UTC 25 Feb 09 08:17:25 AM UTC 25 6345457738 ps
T212 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.4178851528 Feb 09 08:17:21 AM UTC 25 Feb 09 08:17:25 AM UTC 25 410195216 ps
T106 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.1855816567 Feb 09 08:17:27 AM UTC 25 Feb 09 08:17:31 AM UTC 25 219690993 ps
T213 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.3028050728 Feb 09 08:17:24 AM UTC 25 Feb 09 08:17:27 AM UTC 25 18812112 ps
T192 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.791706444 Feb 09 08:17:24 AM UTC 25 Feb 09 08:17:27 AM UTC 25 194595472 ps
T214 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3860772526 Feb 09 08:17:25 AM UTC 25 Feb 09 08:17:28 AM UTC 25 17939921 ps
T15 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.1698863575 Feb 09 08:17:15 AM UTC 25 Feb 09 08:17:28 AM UTC 25 598988038 ps
T215 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.1446481442 Feb 09 08:17:26 AM UTC 25 Feb 09 08:17:29 AM UTC 25 36681420 ps
T169 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.256564372 Feb 09 08:17:25 AM UTC 25 Feb 09 08:17:29 AM UTC 25 323945314 ps
T114 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3285285179 Feb 09 08:17:26 AM UTC 25 Feb 09 08:17:30 AM UTC 25 84096928 ps
T16 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.137696033 Feb 09 08:17:19 AM UTC 25 Feb 09 08:17:32 AM UTC 25 1045443065 ps
T216 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.2255465496 Feb 09 08:17:28 AM UTC 25 Feb 09 08:17:32 AM UTC 25 57896134 ps
T217 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.274070403 Feb 09 08:17:30 AM UTC 25 Feb 09 08:17:32 AM UTC 25 16035071 ps
T218 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.376847207 Feb 09 08:17:31 AM UTC 25 Feb 09 08:17:33 AM UTC 25 23699475 ps
T17 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.3191107079 Feb 09 08:17:31 AM UTC 25 Feb 09 08:17:40 AM UTC 25 1018815032 ps
T219 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.2534988528 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:43 AM UTC 25 17150348 ps
T193 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.3657273914 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:43 AM UTC 25 27192147 ps
T220 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.516367688 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:43 AM UTC 25 17622826 ps
T221 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2514807186 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:43 AM UTC 25 15645243 ps
T222 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3575651861 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:43 AM UTC 25 15401499 ps
T223 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.3860344618 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:43 AM UTC 25 23344766 ps
T115 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3003349334 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:44 AM UTC 25 41889986 ps
T224 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.228174089 Feb 09 08:17:41 AM UTC 25 Feb 09 08:17:44 AM UTC 25 147016779 ps
T225 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.2282205983 Feb 09 08:17:44 AM UTC 25 Feb 09 08:17:47 AM UTC 25 14368809 ps
T204 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.465641758 Feb 09 08:17:44 AM UTC 25 Feb 09 08:17:47 AM UTC 25 22795998 ps
T226 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.12048930 Feb 09 08:17:44 AM UTC 25 Feb 09 08:17:47 AM UTC 25 54496560 ps
T227 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.3817489505 Feb 09 08:17:44 AM UTC 25 Feb 09 08:17:47 AM UTC 25 24711757 ps
T18 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.2920571746 Feb 09 08:16:35 AM UTC 25 Feb 09 08:17:48 AM UTC 25 10964164499 ps
T228 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.1415541255 Feb 09 08:17:48 AM UTC 25 Feb 09 08:17:50 AM UTC 25 30010498 ps
T194 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.4096722475 Feb 09 08:17:48 AM UTC 25 Feb 09 08:17:50 AM UTC 25 50390526 ps
T229 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.2621092766 Feb 09 08:17:48 AM UTC 25 Feb 09 08:17:51 AM UTC 25 40535203 ps
T230 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.2870781307 Feb 09 08:17:44 AM UTC 25 Feb 09 08:17:52 AM UTC 25 487578238 ps
T231 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.3379817857 Feb 09 08:17:49 AM UTC 25 Feb 09 08:17:52 AM UTC 25 161484471 ps
T170 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.198603720 Feb 09 08:17:51 AM UTC 25 Feb 09 08:17:53 AM UTC 25 17471848 ps
T171 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3031431883 Feb 09 08:17:51 AM UTC 25 Feb 09 08:17:53 AM UTC 25 13122700 ps
T116 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.923399402 Feb 09 08:17:51 AM UTC 25 Feb 09 08:17:54 AM UTC 25 71341969 ps
T232 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.3200375740 Feb 09 08:17:52 AM UTC 25 Feb 09 08:17:55 AM UTC 25 16830283 ps
T233 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.2382330862 Feb 09 08:17:54 AM UTC 25 Feb 09 08:17:57 AM UTC 25 18457826 ps
T151 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.3022619145 Feb 09 08:17:56 AM UTC 25 Feb 09 08:17:58 AM UTC 25 30441893 ps
T234 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.4218065790 Feb 09 08:17:54 AM UTC 25 Feb 09 08:17:58 AM UTC 25 190149173 ps
T41 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.148964336 Feb 09 08:17:45 AM UTC 25 Feb 09 08:17:59 AM UTC 25 799400576 ps
T202 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.3853021053 Feb 09 08:17:58 AM UTC 25 Feb 09 08:18:00 AM UTC 25 15636824 ps
T235 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.821890168 Feb 09 08:18:00 AM UTC 25 Feb 09 08:18:02 AM UTC 25 38683516 ps
T236 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.308100764 Feb 09 08:18:01 AM UTC 25 Feb 09 08:18:03 AM UTC 25 54820003 ps
T195 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.31691892 Feb 09 08:18:03 AM UTC 25 Feb 09 08:18:05 AM UTC 25 35488317 ps
T172 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.4121976036 Feb 09 08:17:53 AM UTC 25 Feb 09 08:18:05 AM UTC 25 1448516553 ps
T237 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.242650912 Feb 09 08:18:04 AM UTC 25 Feb 09 08:18:07 AM UTC 25 78339398 ps
T35 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.3514542336 Feb 09 08:16:14 AM UTC 25 Feb 09 08:18:09 AM UTC 25 9988569270 ps
T173 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1324792625 Feb 09 08:18:06 AM UTC 25 Feb 09 08:18:09 AM UTC 25 22826029 ps
T238 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.366627537 Feb 09 08:18:06 AM UTC 25 Feb 09 08:18:09 AM UTC 25 101226633 ps
T239 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.3631618701 Feb 09 08:17:48 AM UTC 25 Feb 09 08:18:10 AM UTC 25 2429357023 ps
T240 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3618432889 Feb 09 08:18:07 AM UTC 25 Feb 09 08:18:10 AM UTC 25 77705553 ps
T36 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.1419853547 Feb 09 08:17:44 AM UTC 25 Feb 09 08:18:11 AM UTC 25 3175809490 ps
T241 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.262177547 Feb 09 08:18:10 AM UTC 25 Feb 09 08:18:12 AM UTC 25 19662226 ps
T242 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.664511054 Feb 09 08:18:11 AM UTC 25 Feb 09 08:18:13 AM UTC 25 21778193 ps
T243 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.2738412401 Feb 09 08:18:11 AM UTC 25 Feb 09 08:18:14 AM UTC 25 50596643 ps
T152 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.913450827 Feb 09 08:18:12 AM UTC 25 Feb 09 08:18:14 AM UTC 25 52651914 ps
T244 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.3510086553 Feb 09 08:18:13 AM UTC 25 Feb 09 08:18:16 AM UTC 25 69672815 ps
T245 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.3635582194 Feb 09 08:18:15 AM UTC 25 Feb 09 08:18:18 AM UTC 25 43709220 ps
T246 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.231177417 Feb 09 08:18:10 AM UTC 25 Feb 09 08:18:18 AM UTC 25 1183649094 ps
T37 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.1346002164 Feb 09 08:17:59 AM UTC 25 Feb 09 08:18:18 AM UTC 25 1162465399 ps
T247 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.2355109712 Feb 09 08:18:17 AM UTC 25 Feb 09 08:18:20 AM UTC 25 66518328 ps
T196 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.121693833 Feb 09 08:18:18 AM UTC 25 Feb 09 08:18:21 AM UTC 25 14824656 ps
T248 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.1053439524 Feb 09 08:18:19 AM UTC 25 Feb 09 08:18:22 AM UTC 25 92462647 ps
T249 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.825220966 Feb 09 08:18:20 AM UTC 25 Feb 09 08:18:22 AM UTC 25 63854643 ps
T250 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2381444207 Feb 09 08:18:21 AM UTC 25 Feb 09 08:18:23 AM UTC 25 38434931 ps
T251 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.1772951258 Feb 09 08:17:59 AM UTC 25 Feb 09 08:18:24 AM UTC 25 1940386489 ps
T252 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.4076813859 Feb 09 08:18:22 AM UTC 25 Feb 09 08:18:24 AM UTC 25 46107955 ps
T253 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.531720434 Feb 09 08:18:23 AM UTC 25 Feb 09 08:18:25 AM UTC 25 35707087 ps
T38 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.2684650466 Feb 09 08:18:14 AM UTC 25 Feb 09 08:18:26 AM UTC 25 2525290700 ps
T254 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.543439460 Feb 09 08:18:25 AM UTC 25 Feb 09 08:18:27 AM UTC 25 51401178 ps
T255 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.2358565884 Feb 09 08:18:23 AM UTC 25 Feb 09 08:18:29 AM UTC 25 870668345 ps
T256 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.3902854734 Feb 09 08:18:26 AM UTC 25 Feb 09 08:18:29 AM UTC 25 93210485 ps
T257 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.1056689832 Feb 09 08:18:27 AM UTC 25 Feb 09 08:18:30 AM UTC 25 26532676 ps
T258 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.79336302 Feb 09 08:18:29 AM UTC 25 Feb 09 08:18:32 AM UTC 25 62612629 ps
T259 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.4117840116 Feb 09 08:18:31 AM UTC 25 Feb 09 08:18:33 AM UTC 25 73455383 ps
T260 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.2110581001 Feb 09 08:18:28 AM UTC 25 Feb 09 08:18:34 AM UTC 25 467268151 ps
T197 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.1685878029 Feb 09 08:18:33 AM UTC 25 Feb 09 08:18:35 AM UTC 25 12757144 ps
T261 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.1012181583 Feb 09 08:18:34 AM UTC 25 Feb 09 08:18:36 AM UTC 25 36162603 ps
T262 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.274618865 Feb 09 08:18:35 AM UTC 25 Feb 09 08:18:37 AM UTC 25 30255803 ps
T263 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1576979944 Feb 09 08:18:36 AM UTC 25 Feb 09 08:18:39 AM UTC 25 56715951 ps
T117 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1356302737 Feb 09 08:18:37 AM UTC 25 Feb 09 08:18:40 AM UTC 25 64757789 ps
T264 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.521878540 Feb 09 08:18:38 AM UTC 25 Feb 09 08:18:41 AM UTC 25 20743267 ps
T265 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.1209430929 Feb 09 08:18:14 AM UTC 25 Feb 09 08:18:41 AM UTC 25 2415511563 ps
T266 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.1243515022 Feb 09 08:18:39 AM UTC 25 Feb 09 08:18:45 AM UTC 25 654279045 ps
T267 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.3388051374 Feb 09 08:18:42 AM UTC 25 Feb 09 08:18:45 AM UTC 25 46367765 ps
T268 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.763468366 Feb 09 08:18:29 AM UTC 25 Feb 09 08:18:47 AM UTC 25 1338902036 ps
T153 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.456811327 Feb 09 08:18:46 AM UTC 25 Feb 09 08:18:48 AM UTC 25 16410539 ps
T269 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.2042823454 Feb 09 08:18:46 AM UTC 25 Feb 09 08:18:48 AM UTC 25 39217639 ps
T42 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.3852095272 Feb 09 08:18:25 AM UTC 25 Feb 09 08:18:49 AM UTC 25 2998563713 ps
T270 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.646622300 Feb 09 08:18:49 AM UTC 25 Feb 09 08:18:51 AM UTC 25 15235483 ps
T271 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.1256435156 Feb 09 08:18:50 AM UTC 25 Feb 09 08:18:52 AM UTC 25 15138119 ps
T272 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.3303880629 Feb 09 08:18:49 AM UTC 25 Feb 09 08:18:53 AM UTC 25 464675171 ps
T273 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.2168191250 Feb 09 08:18:52 AM UTC 25 Feb 09 08:18:55 AM UTC 25 84049042 ps
T274 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.3472937462 Feb 09 08:18:53 AM UTC 25 Feb 09 08:18:55 AM UTC 25 34599491 ps
T275 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1488062800 Feb 09 08:18:54 AM UTC 25 Feb 09 08:18:57 AM UTC 25 15362872 ps
T276 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1661421013 Feb 09 08:18:55 AM UTC 25 Feb 09 08:18:58 AM UTC 25 13316417 ps
T277 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3757739251 Feb 09 08:18:56 AM UTC 25 Feb 09 08:18:59 AM UTC 25 61971409 ps
T278 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.705715669 Feb 09 08:18:57 AM UTC 25 Feb 09 08:19:00 AM UTC 25 13379541 ps
T154 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.671009849 Feb 09 08:18:41 AM UTC 25 Feb 09 08:19:00 AM UTC 25 2431648299 ps
T279 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.2920281585 Feb 09 08:19:01 AM UTC 25 Feb 09 08:19:03 AM UTC 25 14392336 ps
T280 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.1425791579 Feb 09 08:19:01 AM UTC 25 Feb 09 08:19:03 AM UTC 25 33310395 ps
T174 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.943177508 Feb 09 08:18:59 AM UTC 25 Feb 09 08:19:03 AM UTC 25 390603111 ps
T281 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.2459668392 Feb 09 08:19:04 AM UTC 25 Feb 09 08:19:06 AM UTC 25 19706395 ps
T282 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.2546142607 Feb 09 08:19:04 AM UTC 25 Feb 09 08:19:06 AM UTC 25 40384193 ps
T283 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.1593295765 Feb 09 08:19:07 AM UTC 25 Feb 09 08:19:09 AM UTC 25 13554729 ps
T284 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.308497388 Feb 09 08:19:10 AM UTC 25 Feb 09 08:19:14 AM UTC 25 333290588 ps
T285 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.2399218878 Feb 09 08:18:49 AM UTC 25 Feb 09 08:19:15 AM UTC 25 2064930747 ps
T286 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.751316305 Feb 09 08:19:14 AM UTC 25 Feb 09 08:19:17 AM UTC 25 22520523 ps
T287 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.2297659027 Feb 09 08:19:16 AM UTC 25 Feb 09 08:19:19 AM UTC 25 24921417 ps
T288 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2855446258 Feb 09 08:19:18 AM UTC 25 Feb 09 08:19:20 AM UTC 25 62226707 ps
T289 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2255807235 Feb 09 08:19:20 AM UTC 25 Feb 09 08:19:22 AM UTC 25 48949368 ps
T290 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.2011301501 Feb 09 08:19:04 AM UTC 25 Feb 09 08:19:23 AM UTC 25 2472800386 ps
T291 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.1019231709 Feb 09 08:19:21 AM UTC 25 Feb 09 08:19:23 AM UTC 25 37575394 ps
T292 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.3976078710 Feb 09 08:19:07 AM UTC 25 Feb 09 08:19:28 AM UTC 25 1816075384 ps
T293 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.2608398647 Feb 09 08:19:39 AM UTC 25 Feb 09 08:19:41 AM UTC 25 26599837 ps
T294 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.3601856355 Feb 09 08:19:39 AM UTC 25 Feb 09 08:19:42 AM UTC 25 34299075 ps
T295 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.987870172 Feb 09 08:19:39 AM UTC 25 Feb 09 08:19:42 AM UTC 25 38313850 ps
T296 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.3089136140 Feb 09 08:19:39 AM UTC 25 Feb 09 08:19:42 AM UTC 25 23194545 ps
T297 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.4156983108 Feb 09 08:19:39 AM UTC 25 Feb 09 08:19:50 AM UTC 25 969863746 ps
T298 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.4202480726 Feb 09 08:19:56 AM UTC 25 Feb 09 08:19:58 AM UTC 25 41738241 ps
T299 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.1438188300 Feb 09 08:19:56 AM UTC 25 Feb 09 08:19:58 AM UTC 25 17114873 ps
T300 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.1945477951 Feb 09 08:19:56 AM UTC 25 Feb 09 08:19:59 AM UTC 25 32233204 ps
T301 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1378051325 Feb 09 08:19:56 AM UTC 25 Feb 09 08:19:59 AM UTC 25 131274342 ps
T302 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.3921069589 Feb 09 08:19:56 AM UTC 25 Feb 09 08:19:59 AM UTC 25 26854803 ps
T303 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.3904209859 Feb 09 08:19:56 AM UTC 25 Feb 09 08:19:59 AM UTC 25 171744515 ps
T304 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.3295689998 Feb 09 08:19:56 AM UTC 25 Feb 09 08:20:01 AM UTC 25 382263230 ps
T305 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.337521389 Feb 09 08:19:56 AM UTC 25 Feb 09 08:20:01 AM UTC 25 528068480 ps
T306 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.2295100126 Feb 09 08:20:00 AM UTC 25 Feb 09 08:20:02 AM UTC 25 42254890 ps
T307 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.4099571991 Feb 09 08:19:59 AM UTC 25 Feb 09 08:20:02 AM UTC 25 24328172 ps
T308 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.528756802 Feb 09 08:20:00 AM UTC 25 Feb 09 08:20:02 AM UTC 25 23198946 ps
T309 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.597943987 Feb 09 08:19:59 AM UTC 25 Feb 09 08:20:02 AM UTC 25 124905421 ps
T73 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.396029631 Feb 09 08:16:47 AM UTC 25 Feb 09 08:20:02 AM UTC 25 20602774862 ps
T95 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.2826591277 Feb 09 08:20:02 AM UTC 25 Feb 09 08:20:04 AM UTC 25 19562183 ps
T96 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.340645872 Feb 09 08:20:03 AM UTC 25 Feb 09 08:20:05 AM UTC 25 44261079 ps
T97 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.1422162103 Feb 09 08:20:03 AM UTC 25 Feb 09 08:20:06 AM UTC 25 106687549 ps
T98 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.3148262598 Feb 09 08:20:03 AM UTC 25 Feb 09 08:20:06 AM UTC 25 81489225 ps
T99 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.2747351847 Feb 09 08:19:56 AM UTC 25 Feb 09 08:20:06 AM UTC 25 562794283 ps
T100 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.1886573245 Feb 09 08:20:03 AM UTC 25 Feb 09 08:20:06 AM UTC 25 72846913 ps
T101 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.254206531 Feb 09 08:20:05 AM UTC 25 Feb 09 08:20:08 AM UTC 25 145925294 ps
T102 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.780202844 Feb 09 08:20:06 AM UTC 25 Feb 09 08:20:09 AM UTC 25 31567353 ps
T103 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.406394715 Feb 09 08:20:06 AM UTC 25 Feb 09 08:20:09 AM UTC 25 53556784 ps
T310 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.1713386278 Feb 09 08:20:06 AM UTC 25 Feb 09 08:20:09 AM UTC 25 36044243 ps
T311 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.4178896530 Feb 09 08:20:02 AM UTC 25 Feb 09 08:20:10 AM UTC 25 1054102432 ps
T312 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.1099937197 Feb 09 08:20:10 AM UTC 25 Feb 09 08:20:12 AM UTC 25 41493681 ps
T313 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.2058463309 Feb 09 08:20:10 AM UTC 25 Feb 09 08:20:12 AM UTC 25 43469441 ps
T314 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.1884336793 Feb 09 08:20:10 AM UTC 25 Feb 09 08:20:12 AM UTC 25 47475407 ps
T175 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.2039341424 Feb 09 08:20:06 AM UTC 25 Feb 09 08:20:15 AM UTC 25 958805843 ps
T315 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.983600258 Feb 09 08:20:13 AM UTC 25 Feb 09 08:20:15 AM UTC 25 15448659 ps
T316 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.3998450315 Feb 09 08:20:13 AM UTC 25 Feb 09 08:20:16 AM UTC 25 30018992 ps
T317 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.675958987 Feb 09 08:20:03 AM UTC 25 Feb 09 08:20:17 AM UTC 25 2144181420 ps
T318 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.3615539715 Feb 09 08:20:16 AM UTC 25 Feb 09 08:20:19 AM UTC 25 14949923 ps
T319 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.1228747584 Feb 09 08:20:16 AM UTC 25 Feb 09 08:20:19 AM UTC 25 27052418 ps
T320 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1737403590 Feb 09 08:20:16 AM UTC 25 Feb 09 08:20:19 AM UTC 25 21262370 ps
T321 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2166217612 Feb 09 08:20:19 AM UTC 25 Feb 09 08:20:22 AM UTC 25 189259535 ps
T322 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.3200788926 Feb 09 08:20:20 AM UTC 25 Feb 09 08:20:22 AM UTC 25 28713596 ps
T323 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.3370269741 Feb 09 08:20:20 AM UTC 25 Feb 09 08:20:22 AM UTC 25 39840345 ps
T70 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.2184609975 Feb 09 08:19:39 AM UTC 25 Feb 09 08:20:23 AM UTC 25 5860085929 ps
T324 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.1606671237 Feb 09 08:20:23 AM UTC 25 Feb 09 08:20:25 AM UTC 25 48826860 ps
T325 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.3834452243 Feb 09 08:20:24 AM UTC 25 Feb 09 08:20:27 AM UTC 25 20893588 ps
T326 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.3383246775 Feb 09 08:20:13 AM UTC 25 Feb 09 08:20:28 AM UTC 25 1709956497 ps
T327 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.4200807463 Feb 09 08:20:25 AM UTC 25 Feb 09 08:20:28 AM UTC 25 82674208 ps
T328 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.3666135250 Feb 09 08:20:28 AM UTC 25 Feb 09 08:20:31 AM UTC 25 14992574 ps
T329 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.1520599599 Feb 09 08:20:28 AM UTC 25 Feb 09 08:20:31 AM UTC 25 25505886 ps
T330 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.2575743529 Feb 09 08:20:32 AM UTC 25 Feb 09 08:20:34 AM UTC 25 19618272 ps
T331 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.2409244862 Feb 09 08:20:32 AM UTC 25 Feb 09 08:20:35 AM UTC 25 68348279 ps
T134 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.1925591244 Feb 09 08:20:20 AM UTC 25 Feb 09 08:20:36 AM UTC 25 2655350531 ps
T332 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.36712154 Feb 09 08:20:35 AM UTC 25 Feb 09 08:20:37 AM UTC 25 15701507 ps
T333 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.781761061 Feb 09 08:20:36 AM UTC 25 Feb 09 08:20:38 AM UTC 25 74691148 ps
T118 /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3222830905 Feb 09 08:20:37 AM UTC 25 Feb 09 08:20:40 AM UTC 25 247343459 ps
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