Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26025153	1		T1	4683		T2	8524		T3	415
full_word	7764556	1		T1	12488		T2	30935		T3	180

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33789389	1		T1	17171		T2	39459		T3	595
auto[TlIntgErrCmd]	112	1		T179	6		T190	3		T202	7
auto[TlIntgErrData]	102	1		T179	7		T190	1		T202	3
auto[TlIntgErrBoth]	106	1		T179	7		T190	6		T202	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29338134	1		T1	4093		T2	33096		T3	496
auto[1]	4451575	1		T1	13078		T2	6363		T3	99

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25348635	1		T1	2130		T2	6232		T3	392
auto[TlIntgErrNone]	partial	auto[1]	676229	1		T1	2553		T2	2292		T3	23
auto[TlIntgErrNone]	full_word	auto[0]	3989356	1		T1	1963		T2	26864		T3	104
auto[TlIntgErrNone]	full_word	auto[1]	3775169	1		T1	10525		T2	4071		T3	76
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T179	3		T190	2		T202	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T179	1		T190	1		T202	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T359	1		T360	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	12	1		T179	2		T202	1		T350	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T179	3		T202	2		T350	6
auto[TlIntgErrData]	partial	auto[1]	50	1		T179	4		T190	1		T202	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T350	1		T358	1		T352	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T357	1		T356	1		T361	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T179	1		T190	4		T202	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T179	6		T190	2		T202	5
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T202	1		T353	1		T350	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T202	1		T352	1		T355	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22901	1		T59	112		T178	221		T179	16
full_word	4029678	1		T2	16111		T3	7		T4	16552

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4052279	1		T2	16111		T3	7		T4	16552
auto[TlIntgErrCmd]	89	1		T179	8		T190	1		T202	6
auto[TlIntgErrData]	118	1		T179	7		T190	6		T202	4
auto[TlIntgErrBoth]	93	1		T179	2		T190	2		T202	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4023335	1		T2	16111		T3	7		T4	16552
auto[1]	29244	1		T59	171		T178	335		T179	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1560	1		T59	10		T178	19		T188	53
auto[TlIntgErrNone]	partial	auto[1]	21063	1		T59	102		T178	202		T188	514
auto[TlIntgErrNone]	full_word	auto[0]	4021640	1		T2	16111		T3	7		T4	16552
auto[TlIntgErrNone]	full_word	auto[1]	8016	1		T59	69		T178	133		T188	347
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T179	2		T202	2		T353	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T179	6		T190	1		T202	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T357	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T353	1		T351	1		T354	2
auto[TlIntgErrData]	partial	auto[0]	62	1		T179	3		T190	4		T202	1
auto[TlIntgErrData]	partial	auto[1]	48	1		T179	4		T190	2		T202	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T356	1		T362	1		T359	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T353	1		T352	1		T357	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T179	1		T190	1		T202	6
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T190	1		T202	2		T353	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T202	1		T353	1		T362	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T179	1		T363	1		T359	1