Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1617960372	1614514252	0	0
CheckNGreaterZero_A	4100	4100	0	0
GntImpliesReady_A	1617960372	411623898	0	0
GntImpliesValid_A	1617960372	411623898	0	0
GrantKnown_A	1617960372	1614514252	0	0
IdxKnown_A	1617960372	1614514252	0	0
IndexIsCorrect_A	1617960372	411623898	0	0
NoReadyValidNoGrant_A	1617960372	174688602	0	0
Priority_A	1617960372	435672182	0	0
ReadyAndValidImplyGrant_A	1617960372	411623898	0	0
ReqAndReadyImplyGrant_A	1617960372	411623898	0	0
ReqImpliesValid_A	1617960372	435672182	0	0
ValidKnown_A	1617960372	1614514252	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	1614514252	0	0
T1	711440	711412	0	0
T2	468956	468908	0	0
T3	7920	7164	0	0
T4	212016	211740	0	0
T5	3454196	3453520	0	0
T6	3532	3284	0	0
T9	15380	12452	0	0
T16	225560	225360	0	0
T17	10572	10004	0	0
T18	1956480	1956448	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4100	4100	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T9	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	411623898	0	0
T1	711440	1703900	0	0
T2	468956	82878	0	0
T3	7920	464	0	0
T4	212016	45200	0	0
T5	3454196	61872	0	0
T6	3532	518	0	0
T9	15380	364	0	0
T10	0	255794	0	0
T16	225560	28160	0	0
T17	10572	340	0	0
T18	1956480	806162	0	0
T19	0	1384	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	411623898	0	0
T1	711440	1703900	0	0
T2	468956	82878	0	0
T3	7920	464	0	0
T4	212016	45200	0	0
T5	3454196	61872	0	0
T6	3532	518	0	0
T9	15380	364	0	0
T10	0	255794	0	0
T16	225560	28160	0	0
T17	10572	340	0	0
T18	1956480	806162	0	0
T19	0	1384	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	1614514252	0	0
T1	711440	711412	0	0
T2	468956	468908	0	0
T3	7920	7164	0	0
T4	212016	211740	0	0
T5	3454196	3453520	0	0
T6	3532	3284	0	0
T9	15380	12452	0	0
T16	225560	225360	0	0
T17	10572	10004	0	0
T18	1956480	1956448	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	1614514252	0	0
T1	711440	711412	0	0
T2	468956	468908	0	0
T3	7920	7164	0	0
T4	212016	211740	0	0
T5	3454196	3453520	0	0
T6	3532	3284	0	0
T9	15380	12452	0	0
T16	225560	225360	0	0
T17	10572	10004	0	0
T18	1956480	1956448	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	411623898	0	0
T1	711440	1703900	0	0
T2	468956	82878	0	0
T3	7920	464	0	0
T4	212016	45200	0	0
T5	3454196	61872	0	0
T6	3532	518	0	0
T9	15380	364	0	0
T10	0	255794	0	0
T16	225560	28160	0	0
T17	10572	340	0	0
T18	1956480	806162	0	0
T19	0	1384	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	174688602	0	0
T1	355720	3392	0	0
T2	468956	2478378	0	0
T3	7920	1046	0	0
T4	212016	56286	0	0
T5	3454196	2020420	0	0
T6	3532	256	0	0
T9	15380	1344	0	0
T10	0	1048576	0	0
T16	225560	128	0	0
T17	10572	728	0	0
T18	1956480	806656	0	0
T19	0	778	0	0
T26	258112	0	0	0
T27	0	4870	0	0
T53	0	38	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	435672182	0	0
T1	711440	1703900	0	0
T2	468956	624982	0	0
T3	7920	464	0	0
T4	212016	74488	0	0
T5	3454196	528082	0	0
T6	3532	518	0	0
T9	15380	364	0	0
T10	0	255794	0	0
T16	225560	28160	0	0
T17	10572	340	0	0
T18	1956480	806162	0	0
T19	0	1874	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	411623898	0	0
T1	711440	1703900	0	0
T2	468956	82878	0	0
T3	7920	464	0	0
T4	212016	45200	0	0
T5	3454196	61872	0	0
T6	3532	518	0	0
T9	15380	364	0	0
T10	0	255794	0	0
T16	225560	28160	0	0
T17	10572	340	0	0
T18	1956480	806162	0	0
T19	0	1384	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	411623898	0	0
T1	711440	1703900	0	0
T2	468956	82878	0	0
T3	7920	464	0	0
T4	212016	45200	0	0
T5	3454196	61872	0	0
T6	3532	518	0	0
T9	15380	364	0	0
T10	0	255794	0	0
T16	225560	28160	0	0
T17	10572	340	0	0
T18	1956480	806162	0	0
T19	0	1384	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	435672182	0	0
T1	711440	1703900	0	0
T2	468956	624982	0	0
T3	7920	464	0	0
T4	212016	74488	0	0
T5	3454196	528082	0	0
T6	3532	518	0	0
T9	15380	364	0	0
T10	0	255794	0	0
T16	225560	28160	0	0
T17	10572	340	0	0
T18	1956480	806162	0	0
T19	0	1874	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1617960372	1614514252	0	0
T1	711440	711412	0	0
T2	468956	468908	0	0
T3	7920	7164	0	0
T4	212016	211740	0	0
T5	3454196	3453520	0	0
T6	3532	3284	0	0
T9	15380	12452	0	0
T16	225560	225360	0	0
T17	10572	10004	0	0
T18	1956480	1956448	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404490093	403628563	0	0
CheckNGreaterZero_A	1025	1025	0	0
GntImpliesReady_A	404490093	110980054	0	0
GntImpliesValid_A	404490093	110980054	0	0
GrantKnown_A	404490093	403628563	0	0
IdxKnown_A	404490093	403628563	0	0
IndexIsCorrect_A	404490093	110980054	0	0
NoReadyValidNoGrant_A	404490093	45540298	0	0
Priority_A	404490093	116989247	0	0
ReadyAndValidImplyGrant_A	404490093	110980054	0	0
ReqAndReadyImplyGrant_A	404490093	110980054	0	0
ReqImpliesValid_A	404490093	116989247	0	0
ValidKnown_A	404490093	403628563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980054	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980054	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980054	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	45540298	0	0
T1	177860	1696	0	0
T2	117239	665011	0	0
T3	1980	502	0	0
T4	53004	13154	0	0
T5	863549	521253	0	0
T6	883	128	0	0
T9	3845	672	0	0
T16	56390	64	0	0
T17	2643	352	0	0
T18	489120	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	116989247	0	0
T1	177860	100122	0	0
T2	117239	154379	0	0
T3	1980	226	0	0
T4	53004	18766	0	0
T5	863549	145470	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980054	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980054	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	116989247	0	0
T1	177860	100122	0	0
T2	117239	154379	0	0
T3	1980	226	0	0
T4	53004	18766	0	0
T5	863549	145470	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404490093	403628563	0	0
CheckNGreaterZero_A	1025	1025	0	0
GntImpliesReady_A	404490093	110980060	0	0
GntImpliesValid_A	404490093	110980060	0	0
GrantKnown_A	404490093	403628563	0	0
IdxKnown_A	404490093	403628563	0	0
IndexIsCorrect_A	404490093	110980060	0	0
NoReadyValidNoGrant_A	404490093	45540233	0	0
Priority_A	404490093	116989318	0	0
ReadyAndValidImplyGrant_A	404490093	110980060	0	0
ReqAndReadyImplyGrant_A	404490093	110980060	0	0
ReqImpliesValid_A	404490093	116989318	0	0
ValidKnown_A	404490093	403628563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980060	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980060	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980060	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	45540233	0	0
T1	177860	1696	0	0
T2	117239	665011	0	0
T3	1980	502	0	0
T4	53004	13154	0	0
T5	863549	521253	0	0
T6	883	128	0	0
T9	3845	672	0	0
T16	56390	64	0	0
T17	2643	352	0	0
T18	489120	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	116989318	0	0
T1	177860	100122	0	0
T2	117239	154379	0	0
T3	1980	226	0	0
T4	53004	18766	0	0
T5	863549	145470	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980060	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	110980060	0	0
T1	177860	100122	0	0
T2	117239	22349	0	0
T3	1980	226	0	0
T4	53004	10943	0	0
T5	863549	16065	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	116989318	0	0
T1	177860	100122	0	0
T2	117239	154379	0	0
T3	1980	226	0	0
T4	53004	18766	0	0
T5	863549	145470	0	0
T6	883	32	0	0
T9	3845	182	0	0
T16	56390	14080	0	0
T17	2643	164	0	0
T18	489120	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404490093	403628563	0	0
CheckNGreaterZero_A	1025	1025	0	0
GntImpliesReady_A	404490093	94831889	0	0
GntImpliesValid_A	404490093	94831889	0	0
GrantKnown_A	404490093	403628563	0	0
IdxKnown_A	404490093	403628563	0	0
IndexIsCorrect_A	404490093	94831889	0	0
NoReadyValidNoGrant_A	404490093	41804070	0	0
Priority_A	404490093	100846771	0	0
ReadyAndValidImplyGrant_A	404490093	94831889	0	0
ReqAndReadyImplyGrant_A	404490093	94831889	0	0
ReqImpliesValid_A	404490093	100846771	0	0
ValidKnown_A	404490093	403628563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831889	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831889	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831889	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	41804070	0	0
T2	117239	574178	0	0
T3	1980	21	0	0
T4	53004	14989	0	0
T5	863549	488957	0	0
T6	883	0	0	0
T9	3845	0	0	0
T10	0	524288	0	0
T16	56390	0	0	0
T17	2643	12	0	0
T18	489120	403200	0	0
T19	0	389	0	0
T26	129056	0	0	0
T27	0	2435	0	0
T53	0	19	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	100846771	0	0
T1	177860	751828	0	0
T2	117239	158112	0	0
T3	1980	6	0	0
T4	53004	18478	0	0
T5	863549	118571	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	937	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831889	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831889	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	100846771	0	0
T1	177860	751828	0	0
T2	117239	158112	0	0
T3	1980	6	0	0
T4	53004	18478	0	0
T5	863549	118571	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	937	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	404490093	403628563	0	0
CheckNGreaterZero_A	1025	1025	0	0
GntImpliesReady_A	404490093	94831895	0	0
GntImpliesValid_A	404490093	94831895	0	0
GrantKnown_A	404490093	403628563	0	0
IdxKnown_A	404490093	403628563	0	0
IndexIsCorrect_A	404490093	94831895	0	0
NoReadyValidNoGrant_A	404490093	41804001	0	0
Priority_A	404490093	100846846	0	0
ReadyAndValidImplyGrant_A	404490093	94831895	0	0
ReqAndReadyImplyGrant_A	404490093	94831895	0	0
ReqImpliesValid_A	404490093	100846846	0	0
ValidKnown_A	404490093	403628563	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831895	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831895	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831895	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	41804001	0	0
T2	117239	574178	0	0
T3	1980	21	0	0
T4	53004	14989	0	0
T5	863549	488957	0	0
T6	883	0	0	0
T9	3845	0	0	0
T10	0	524288	0	0
T16	56390	0	0	0
T17	2643	12	0	0
T18	489120	403200	0	0
T19	0	389	0	0
T26	129056	0	0	0
T27	0	2435	0	0
T53	0	19	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	100846846	0	0
T1	177860	751828	0	0
T2	117239	158112	0	0
T3	1980	6	0	0
T4	53004	18478	0	0
T5	863549	118571	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	937	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831895	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	94831895	0	0
T1	177860	751828	0	0
T2	117239	19090	0	0
T3	1980	6	0	0
T4	53004	11657	0	0
T5	863549	14871	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	692	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	100846846	0	0
T1	177860	751828	0	0
T2	117239	158112	0	0
T3	1980	6	0	0
T4	53004	18478	0	0
T5	863549	118571	0	0
T6	883	227	0	0
T9	3845	0	0	0
T10	0	127897	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	403049	0	0
T19	0	937	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0