Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.52	100.00	90.09			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.47	100.00	89.87			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.52	100.00	90.09			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.47	100.00	89.87			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.57	99.17	93.18	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.52	100.00	90.09			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.59	99.17	93.26	100.00		99.28	96.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
u_bus_intg	100.00	100.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	454	409	90.09
Logical	454	409	90.09
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-703	90.64
706-710	75.00

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T55,T152
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T81
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	808980186	1588033	0	0
ExclusiveOps_A	808980186	807257126	0	0
ExclusiveProgHazard_A	808980186	807257126	0	0
ExclusiveState_A	808980186	807257126	0	0
ForwardCheck_A	808980186	3584194	0	0
IdleCheck_A	808980186	100553206	0	0
MaxBufs_A	2050	2050	0	0
OneHotAlloc_A	808980186	807257126	0	0
OneHotMatch_A	808980186	807257126	0	0
OneHotRspMatch_A	808980186	807257126	0	0
OneHotUpdate_A	808980186	807257126	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	1588033	0	0
T2	234478	11910	0	0
T3	3960	47	0	0
T4	106008	2237	0	0
T5	1727098	6556	0	0
T6	1766	0	0	0
T9	7690	0	0	0
T16	112780	0	0	0
T17	5286	18	0	0
T18	978240	134400	0	0
T19	0	181	0	0
T22	0	21	0	0
T23	0	86	0	0
T26	258112	0	0	0
T27	0	1094	0	0
T32	0	1676	0	0
T50	0	15	0	0
T53	0	5	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	807257126	0	0
T1	355720	355706	0	0
T2	234478	234454	0	0
T3	3960	3582	0	0
T4	106008	105870	0	0
T5	1727098	1726760	0	0
T6	1766	1642	0	0
T9	7690	6226	0	0
T16	112780	112680	0	0
T17	5286	5002	0	0
T18	978240	978224	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	807257126	0	0
T1	355720	355706	0	0
T2	234478	234454	0	0
T3	3960	3582	0	0
T4	106008	105870	0	0
T5	1727098	1726760	0	0
T6	1766	1642	0	0
T9	7690	6226	0	0
T16	112780	112680	0	0
T17	5286	5002	0	0
T18	978240	978224	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	807257126	0	0
T1	355720	355706	0	0
T2	234478	234454	0	0
T3	3960	3582	0	0
T4	106008	105870	0	0
T5	1727098	1726760	0	0
T6	1766	1642	0	0
T9	7690	6226	0	0
T16	112780	112680	0	0
T17	5286	5002	0	0
T18	978240	978224	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	3584194	0	0
T2	234478	29465	0	0
T3	3960	0	0	0
T4	106008	19806	0	0
T5	1727098	24343	0	0
T6	1766	0	0	0
T9	7690	0	0	0
T16	112780	32	0	0
T17	5286	9	0	0
T18	978240	134400	0	0
T22	0	9	0	0
T23	0	17	0	0
T26	258112	32	0	0
T27	0	1108	0	0
T32	0	13612	0	0
T53	0	7	0	0
T82	0	74	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	100553206	0	0
T1	177860	1696	0	0
T2	234478	1518017	0	0
T3	3960	523	0	0
T4	106008	41977	0	0
T5	1727098	1249967	0	0
T6	1766	128	0	0
T9	7690	672	0	0
T10	0	524288	0	0
T16	112780	64	0	0
T17	5286	364	0	0
T18	978240	403328	0	0
T19	0	573	0	0
T26	129056	0	0	0
T27	0	2435	0	0
T53	0	19	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2050	2050	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T9	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	807257126	0	0
T1	355720	355706	0	0
T2	234478	234454	0	0
T3	3960	3582	0	0
T4	106008	105870	0	0
T5	1727098	1726760	0	0
T6	1766	1642	0	0
T9	7690	6226	0	0
T16	112780	112680	0	0
T17	5286	5002	0	0
T18	978240	978224	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	807257126	0	0
T1	355720	355706	0	0
T2	234478	234454	0	0
T3	3960	3582	0	0
T4	106008	105870	0	0
T5	1727098	1726760	0	0
T6	1766	1642	0	0
T9	7690	6226	0	0
T16	112780	112680	0	0
T17	5286	5002	0	0
T18	978240	978224	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	807257126	0	0
T1	355720	355706	0	0
T2	234478	234454	0	0
T3	3960	3582	0	0
T4	106008	105870	0	0
T5	1727098	1726760	0	0
T6	1766	1642	0	0
T9	7690	6226	0	0
T16	112780	112680	0	0
T17	5286	5002	0	0
T18	978240	978224	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808980186	807257126	0	0
T1	355720	355706	0	0
T2	234478	234454	0	0
T3	3960	3582	0	0
T4	106008	105870	0	0
T5	1727098	1726760	0	0
T6	1766	1642	0	0
T9	7690	6226	0	0
T16	112780	112680	0	0
T17	5286	5002	0	0
T18	978240	978224	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	454	408	89.87
Logical	454	408	89.87
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	90.25
706-710	76.92

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T55,T152
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T17,T81
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	404490093	962641	0	0
ExclusiveOps_A	404490093	403628563	0	0
ExclusiveProgHazard_A	404490093	403628563	0	0
ExclusiveState_A	404490093	403628563	0	0
ForwardCheck_A	404490093	1968137	0	0
IdleCheck_A	404490093	52145889	0	0
MaxBufs_A	1025	1025	0	0
OneHotAlloc_A	404490093	403628563	0	0
OneHotMatch_A	404490093	403628563	0	0
OneHotRspMatch_A	404490093	403628563	0	0
OneHotUpdate_A	404490093	403628563	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	962641	0	0
T2	117239	6783	0	0
T3	1980	46	0	0
T4	53004	727	0	0
T5	863549	3304	0	0
T6	883	0	0	0
T9	3845	0	0	0
T16	56390	0	0	0
T17	2643	18	0	0
T18	489120	0	0	0
T19	0	127	0	0
T22	0	21	0	0
T23	0	86	0	0
T26	129056	0	0	0
T27	0	287	0	0
T32	0	764	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	1968137	0	0
T2	117239	15502	0	0
T3	1980	0	0	0
T4	53004	9916	0	0
T5	863549	12724	0	0
T6	883	0	0	0
T9	3845	0	0	0
T16	56390	32	0	0
T17	2643	3	0	0
T18	489120	0	0	0
T22	0	9	0	0
T23	0	2	0	0
T26	129056	32	0	0
T27	0	294	0	0
T32	0	4552	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	52145889	0	0
T1	177860	1696	0	0
T2	117239	800777	0	0
T3	1980	502	0	0
T4	53004	20687	0	0
T5	863549	654146	0	0
T6	883	128	0	0
T9	3845	672	0	0
T16	56390	64	0	0
T17	2643	352	0	0
T18	489120	128	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		124	124	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	256	4	4	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
ALWAYS	359	12	12	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	577	6	6	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	646	6	6	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
136	1	1
139	4	4
140	4	4
145	4	4
151	1	1
153	3	3
185	1	1
192	4	4
193	4	4
195	4	4
211	4	4
217	4	4
221	4	4
228	1	1
231	1	1
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
290	1	1
291	1	1
301	1	1
304	1	1
307	1	1
325	1	1
330	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
381	1	1
392	1	1
398	1	1
406	1	1
427	1	1
431	1	1
441	1	1
444	1	1
450	1	1
455	1	1
458	1	1
488	1	1
491	1	1
494	1	1
498	1	1
500	1	1
501	1	1
502	1	1
510	1	1
518	1	1
520	1	1
574	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
			MISSING_ELSE
587	1	1
591	1	1
594	1	1
601	1	1
605	1	1
613	1	1
630	1	1
635	1	1
640	4	4
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
			MISSING_ELSE
657	1	1
669	1	1
670	1	1
691	1	1
703	1	1
706	1	1
710	1	1
713	1	1
716	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	454	409	90.09
Logical	454	409	90.09
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
139-706	90.48
706-710	76.92

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	185	2	2	100.00
TERNARY	231	2	2	100.00
TERNARY	301	2	2	100.00
TERNARY	450	2	2	100.00
TERNARY	510	3	3	100.00
TERNARY	601	3	3	100.00
TERNARY	605	3	3	100.00
TERNARY	630	3	3	100.00
TERNARY	657	2	2	100.00
TERNARY	691	2	2	100.00
TERNARY	670	2	2	100.00
TERNARY	166	2	2	100.00
IF	256	3	3	100.00
IF	359	4	4	100.00
IF	577	4	4	100.00
IF	649	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	231	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	301	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	450	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T32,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	(hint_descram) ? 
-2-:	510	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T10,T19
0	1	Covered	T4,T152,T157
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	601	(forward) ? 
-2-:	601	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T17
0	1	Covered	T3,T10,T19
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	605	(forward) ? 
-2-:	605	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T17
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T4,T17

	LineNo.	Expression
-1-:	630	(forward) ? 
-2-:	630	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T17
0	1	Covered	T3,T10,T19
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	657	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	691	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	670	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T85
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if (rd_start)
-3-:	370	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	577	if ((!rst_ni))
-2-:	579	if (calc_req_start)
-3-:	581	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T10
0	0	1	Covered	T3,T4,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	404490093	625392	0	0
ExclusiveOps_A	404490093	403628563	0	0
ExclusiveProgHazard_A	404490093	403628563	0	0
ExclusiveState_A	404490093	403628563	0	0
ForwardCheck_A	404490093	1616057	0	0
IdleCheck_A	404490093	48407317	0	0
MaxBufs_A	1025	1025	0	0
OneHotAlloc_A	404490093	403628563	0	0
OneHotMatch_A	404490093	403628563	0	0
OneHotRspMatch_A	404490093	403628563	0	0
OneHotUpdate_A	404490093	403628563	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	625392	0	0
T2	117239	5127	0	0
T3	1980	1	0	0
T4	53004	1510	0	0
T5	863549	3252	0	0
T6	883	0	0	0
T9	3845	0	0	0
T16	56390	0	0	0
T17	2643	0	0	0
T18	489120	134400	0	0
T19	0	54	0	0
T26	129056	0	0	0
T27	0	807	0	0
T32	0	912	0	0
T50	0	15	0	0
T53	0	5	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	1616057	0	0
T2	117239	13963	0	0
T3	1980	0	0	0
T4	53004	9890	0	0
T5	863549	11619	0	0
T6	883	0	0	0
T9	3845	0	0	0
T16	56390	0	0	0
T17	2643	6	0	0
T18	489120	134400	0	0
T23	0	15	0	0
T26	129056	0	0	0
T27	0	814	0	0
T32	0	9060	0	0
T53	0	7	0	0
T82	0	74	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	48407317	0	0
T2	117239	717240	0	0
T3	1980	21	0	0
T4	53004	21290	0	0
T5	863549	595821	0	0
T6	883	0	0	0
T9	3845	0	0	0
T10	0	524288	0	0
T16	56390	0	0	0
T17	2643	12	0	0
T18	489120	403200	0	0
T19	0	573	0	0
T26	129056	0	0	0
T27	0	2435	0	0
T53	0	19	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404490093	403628563	0	0
T1	177860	177853	0	0
T2	117239	117227	0	0
T3	1980	1791	0	0
T4	53004	52935	0	0
T5	863549	863380	0	0
T6	883	821	0	0
T9	3845	3113	0	0
T16	56390	56340	0	0
T17	2643	2501	0	0
T18	489120	489112	0	0