FLASH_CTRL Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.740m	64.495us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.390s	21.601us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.470s	44.493us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.280s	529.456us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.415m	3.255ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	56.810s	1.660ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.230s	1.303ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.280s	529.456us	20	20	100.00
		flash_ctrl_csr_aliasing	56.810s	1.660ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.590s	73.488us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.850s	16.082us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.350s	393.752us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.732m	57.817us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.472m	233.940ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.980m	170.182ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.900s	25.829us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	50.647m	302.857ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.377m	2.701ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.765m	2.545ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.327h	376.603ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.231m	1.359ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.960s	122.439us	28	40	70.00
		flash_ctrl_rw_evict_all_en	32.880s	50.542us	38	40	95.00
		flash_ctrl_re_evict	39.770s	116.975us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.532m	8.129ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.532m	8.129ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.543m	162.554ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.770s	397.539us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.018m	815.110us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	48.919m	40.022ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.044m	406.944us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	42.128m	1.783ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.060s	15.896us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.999m	2.617ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.960s	36.145us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.210s	29.727us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.036m	1.910ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.822m	8.747ms	50	50	100.00
		flash_ctrl_otp_reset	2.298m	470.426us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.472m	233.940ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.495m	1.676ms	39	40	97.50
		flash_ctrl_intr_wr	1.384m	4.923ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.726m	51.034ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.899m	428.616ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.937m	6.070ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.227m	3.078ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.290s	221.788us	5	5	100.00
		flash_ctrl_ro_derr	3.162m	607.810us	10	10	100.00
		flash_ctrl_rw_derr	13.638m	5.366ms	5	10	50.00
		flash_ctrl_derr_detect	1.791m	344.958us	5	5	100.00
		flash_ctrl_integrity	12.337m	36.675ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.880s	44.816us	3	5	60.00
		flash_ctrl_ro_serr	2.987m	2.308ms	10	10	100.00
		flash_ctrl_rw_serr	12.868m	8.674ms	8	10	80.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.782m	3.552ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.363m	888.829us	4	5	80.00
V2	scramble	flash_ctrl_wo	4.273m	7.576ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.330s	4.513us	0	1	0.00
		flash_ctrl_read_word_sweep	14.180s	85.082us	1	1	100.00
		flash_ctrl_ro	2.435m	1.312ms	20	20	100.00
		flash_ctrl_rw	13.137m	74.011ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	41.290s	530.007us	0	5	0.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.314m	104.452ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.612m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.380s	96.606us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.900s	17.886us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.500s	117.409us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.500s	117.409us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.470s	44.493us	5	5	100.00
		flash_ctrl_csr_rw	18.280s	529.456us	20	20	100.00
		flash_ctrl_csr_aliasing	56.810s	1.660ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.150s	449.702us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.470s	44.493us	5	5	100.00
		flash_ctrl_csr_rw	18.280s	529.456us	20	20	100.00
		flash_ctrl_csr_aliasing	56.810s	1.660ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.150s	449.702us	20	20	100.00
V2		TOTAL			977	1013	96.45
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.030s	12.018us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.030s	12.018us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.030s	12.018us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.030s	12.018us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.930s	15.402us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.234m	1.307ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.234m	1.307ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.234m	1.307ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.250s	213.724us	3	3	100.00
		flash_ctrl_wr_intg	15.160s	57.525us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.740m	64.495us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.298m	470.426us	80	80	100.00
		flash_ctrl_disable	22.960s	36.145us	50	50	100.00
		flash_ctrl_sec_info_access	1.492m	9.083ms	50	50	100.00
		flash_ctrl_connect	16.210s	29.727us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.120s	36.451us	3	5	60.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.280s	529.456us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.030s	12.018us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.280s	529.456us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.030s	12.018us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.280s	529.456us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.030s	12.018us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.960s	36.145us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.250s	213.724us	3	3	100.00
		flash_ctrl_access_after_disable	13.940s	177.052us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.960s	36.145us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.770s	397.539us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	13.137m	74.011ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.868m	8.674ms	8	10	80.00
		flash_ctrl_rw_derr	13.638m	5.366ms	5	10	50.00
		flash_ctrl_integrity	12.337m	36.675ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.472m	233.940ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.990s	728.109us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.330s	36.536us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	23.000s	585.616us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.400h	3.393ms	5	5	100.00
V2S		TOTAL			142	144	98.61
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.790s	75.919us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1240	1278	97.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	43	78.18
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.59	95.85	94.24	98.85	92.52	98.31	98.30	98.06

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 14 failures:

Test flash_ctrl_rw_evict has 12 failures.

1.flash_ctrl_rw_evict.19797967907925436514763345406007138330722048907326088878139542841165980827151
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 160546.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0002d0c8
  UVM_INFO @ 160546.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_rw_evict.49225794040627658303044748131896982023288597214004955511319477114902148450283
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 24865.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004198
  UVM_INFO @ 24865.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test flash_ctrl_rw_evict_all_en has 2 failures.

7.flash_ctrl_rw_evict_all_en.98012592553901419565737854627795127976947853151878781597235246065586780161912
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 48145.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000dbed8
  UVM_INFO @ 48145.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.flash_ctrl_rw_evict_all_en.2203010155429855543692546455568827785971215593217143895361134306338057235900
Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 28988.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00065f88
  UVM_INFO @ 28988.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 6 failures:

Test flash_ctrl_read_word_sweep_serr has 2 failures.

0.flash_ctrl_read_word_sweep_serr.35556896620471265504192187771562364054839500822483005487983844350470426316347
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest/run.log

  UVM_ERROR @ 4900.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 4900.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_read_word_sweep_serr.69344514386028030995240280785101971055280219720851939642708293312279988487935
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest/run.log

  UVM_ERROR @ 19290.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 19290.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_fs_sup has 4 failures.

0.flash_ctrl_fs_sup.97656542621452846052808664726080961496551932145428772418602903859443953814075
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log

  UVM_ERROR @ 251192.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 251192.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_fs_sup.36591855599630539423655521785102174261337699164322916925241334707035586145711
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest/run.log

  UVM_ERROR @ 530006.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 530006.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 0.flash_ctrl_rw_derr.95979347798441402625045631139027271910040388431916113554292159365922566830139
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  Job ID: smart:6834e558-107f-4f5b-a79b-52984cfe76f4
```
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.54617271096416125306504422806288719912031157034480789965750964592902424319125
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:e9291df9-8445-49ba-8034-52728bc3ddf4
```
- Test flash_ctrl_rw has 2 failures.
  - 3.flash_ctrl_rw.58500757002451968495851172569364809351184547623702165848042779454571676828816
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:1e9de6aa-258c-4f57-a9aa-084beeb1eaae
```
  - 6.flash_ctrl_rw.62675965844023185336177937634952851624380145070362613660200182223191388491997
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:3a28af60-1e30-4038-bf80-5e4032f88ffe
```
- Test flash_ctrl_oversize_error has 1 failures.
  - 4.flash_ctrl_oversize_error.45148148442548200423188383170385457681937064788941522769048288241224326188186
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest/run.log
```
  Job ID: smart:98f43dc0-7458-4cba-9928-34367a11b1b1
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_rw_derr has 2 failures.

1.flash_ctrl_rw_derr.83257597234875630667866337029386274089189437026943018473225859944946309272187
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 16948150.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (38004925942732259674562 [0x80c404c4230000149c2] vs 38004925951528352696770 [0x80c404c4a30000149c2])
  UVM_INFO @ 16948150.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_derr.28128954497596421130617459610160158013436913894773928960768624390150334365904
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 5550698.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (1494222317562437582855 [0x51008011180a044007] vs 1494231324761692323847 [0x5100a011180a044007])
  UVM_INFO @ 5550698.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_integrity has 1 failures.

3.flash_ctrl_integrity.98247620117462006939042217702484701587166392766604286021074888136219078395524
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 3250155.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (9555427787733514125573 [0x2060033021e10cd0105] vs 68594229949236711309328 [0xe86802b07065314c010])
  UVM_INFO @ 3250155.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_serr_address has 1 failures.
  - 0.flash_ctrl_serr_address.52705365854348604911093999252546839052350138484969053051106680102250988704138
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log
```
  UVM_ERROR @ 1353548.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1353548.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_serr has 1 failures.
  - 5.flash_ctrl_rw_serr.96298141701148059189295234607174936965165083870500645270118238297029383626919
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 5404516.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 5404516.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test flash_ctrl_config_regwen has 2 failures.
  - 0.flash_ctrl_config_regwen.112607113071783087384541393813534961362831930054322472726015707975761414521652
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.flash_ctrl_config_regwen.65686972629207978506252627540177824663357887891887307564458727488520713888436
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_derr has 2 failures.

3.flash_ctrl_rw_derr.86676184413210054970500810359779623019334524050772217600322091783541818316291
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 7735936.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (3530985662972248130 [0x310094c0a4754042] vs 3530985662972379202 [0x310094c0a4774042])
  UVM_INFO @ 7735936.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_rw_derr.30376460359726243324504889986299594714562428752336387521726209836445503301579
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 9785273.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (39720488941725032120352 [0x8694084645440080020] vs 39715877255706604732448 [0x8690084645440080020])
  UVM_INFO @ 9785273.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_write_word_sweep_vseq.sv:22) [flash_ctrl_write_word_sweep_vseq] Check failed mywd == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.73370727892538407494750012202943647180599152586045512846283381023850746577289
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 4513.5 ns: (flash_ctrl_write_word_sweep_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed mywd == 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 4513.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 1.flash_ctrl_integrity.113747449808031738308045673339001259178558265919189189179525600502201273489430
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2450305.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000730
  UVM_INFO @ 2450305.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_bkdr_util.sv:197) [mem_bkdr_util[FlashPartInfo][*]] addr * is out of bounds: size = * has 1 failures:
- Test flash_ctrl_fs_sup has 1 failures.
  - 3.flash_ctrl_fs_sup.107234768198723555317994607215685901526089162032249629716376365010949037882165
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest/run.log
```
  UVM_ERROR @ 257703.2 ns: (mem_bkdr_util.sv:197) [mem_bkdr_util[FlashPartInfo][0]] addr 5000 is out of bounds: size = 5000
  UVM_INFO @ 257703.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp e62715be_1769b177:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 39.flash_ctrl_intr_rd.9782930731983337019801336025873264143121116254927952586239595949518674530250
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 533119.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    e62715be_1769b177:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 533119.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```