FLASH_CTRL Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.327m	35.584us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	48.230s	54.599us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.327m	140.830us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	31.980s	710.437us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.493m	2.197ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.365m	415.906us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	35.280s	45.620us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	31.980s	710.437us	20	20	100.00
		flash_ctrl_csr_aliasing	1.365m	415.906us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	24.700s	21.563us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	25.330s	16.225us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	49.820s	39.890us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	3.392m	63.404us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.848m	878.871ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.023m	50.131ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.560s	15.855us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	56.058m	264.660ms	4	5	80.00
V2	erase_suspend	flash_ctrl_erase_suspend	11.443m	33.372ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.725m	9.487ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.104h	48.915ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.576m	102.660us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.013m	40.804us	38	40	95.00
		flash_ctrl_rw_evict_all_en	1.018m	27.513us	35	40	87.50
		flash_ctrl_re_evict	1.087m	293.704us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.519m	5.510ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.519m	5.510ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.132m	34.440ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	45.850s	1.535ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	28.950m	821.852us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	53.839m	3.667ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	23.087m	3.263ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	57.861m	1.393ms	4	5	80.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	28.760s	18.670us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.504m	12.343ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	45.160s	11.852us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.220s	16.616us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	21.358m	3.316ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.839m	16.353ms	50	50	100.00
		flash_ctrl_otp_reset	3.867m	311.413us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.848m	878.871ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.525m	1.938ms	40	40	100.00
		flash_ctrl_intr_wr	1.966m	2.966ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.643m	48.882ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.837m	25.409ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	2.254m	16.922ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.129m	1.657ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	39.890s	75.260us	5	5	100.00
		flash_ctrl_ro_derr	2.850m	1.307ms	10	10	100.00
		flash_ctrl_rw_derr	4.707m	4.461ms	10	10	100.00
		flash_ctrl_derr_detect	4.038m	2.831ms	5	5	100.00
		flash_ctrl_integrity	23.350m	200.000ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	41.690s	80.051us	5	5	100.00
		flash_ctrl_ro_serr	2.908m	747.498us	10	10	100.00
		flash_ctrl_rw_serr	4.512m	2.111ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.618m	3.389ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.549m	1.900ms	5	5	100.00
V2	scramble	flash_ctrl_wo	19.382m	200.000ms	19	20	95.00
		flash_ctrl_write_word_sweep	26.980s	45.222us	1	1	100.00
		flash_ctrl_read_word_sweep	25.790s	41.455us	1	1	100.00
		flash_ctrl_ro	2.596m	525.028us	19	20	95.00
		flash_ctrl_rw	9.612m	17.354ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	52.140s	994.582us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	24.494m	89.653ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.888m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	29.490s	177.549us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	25.780s	47.669us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	35.540s	61.776us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	35.540s	61.776us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.327m	140.830us	5	5	100.00
		flash_ctrl_csr_rw	31.980s	710.437us	20	20	100.00
		flash_ctrl_csr_aliasing	1.365m	415.906us	5	5	100.00
		flash_ctrl_same_csr_outstanding	57.300s	337.853us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.327m	140.830us	5	5	100.00
		flash_ctrl_csr_rw	31.980s	710.437us	20	20	100.00
		flash_ctrl_csr_aliasing	1.365m	415.906us	5	5	100.00
		flash_ctrl_same_csr_outstanding	57.300s	337.853us	20	20	100.00
V2		TOTAL			997	1013	98.42
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	29.340s	14.567us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	29.340s	14.567us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	29.340s	14.567us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	29.340s	14.567us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	29.310s	86.530us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
		flash_ctrl_tl_intg_err	23.753m	3.433ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	23.753m	3.433ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	23.753m	3.433ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	49.970s	154.363us	3	3	100.00
		flash_ctrl_wr_intg	28.600s	156.493us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.327m	35.584us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	3.867m	311.413us	80	80	100.00
		flash_ctrl_disable	45.160s	11.852us	50	50	100.00
		flash_ctrl_sec_info_access	1.914m	922.410us	50	50	100.00
		flash_ctrl_connect	32.220s	16.616us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	28.030s	20.082us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	31.980s	710.437us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	29.340s	14.567us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	31.980s	710.437us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	29.340s	14.567us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	31.980s	710.437us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	29.340s	14.567us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	45.160s	11.852us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	49.970s	154.363us	3	3	100.00
		flash_ctrl_access_after_disable	25.670s	40.352us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	51.530s	27.562us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	45.160s	11.852us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	45.850s	1.535ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.612m	17.354ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.512m	2.111ms	10	10	100.00
		flash_ctrl_rw_derr	4.707m	4.461ms	10	10	100.00
		flash_ctrl_integrity	23.350m	200.000ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.848m	878.871ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	36.760s	776.567us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	26.230s	17.142us	3	5	60.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	28.440s	17.693us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.898h	6.463ms	5	5	100.00
V2S		TOTAL			145	147	98.64
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.097m	146.485us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1263	1281	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.73	95.23	93.61	97.22	91.84	97.05	97.00	98.18

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 7 failures:

Test flash_ctrl_rw_evict_all_en has 5 failures.

2.flash_ctrl_rw_evict_all_en.112390621079202430121645118580337081094786264581588615394107230832230675183813
Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 14458.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 14458.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.flash_ctrl_rw_evict_all_en.98610572812740178007532674500836839687434410470461011238148748029366896302816
Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 17434.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 17434.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test flash_ctrl_rw_evict has 2 failures.

7.flash_ctrl_rw_evict.115059550384810714069301027167216293997733924476981226086046406852666912778876
Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 21071.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 21071.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.flash_ctrl_rw_evict.77118098446517220564656182459529222554931875987821443800072320500485966682959
Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 14556.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 14556.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job timed out after * minutes has 6 failures:
- Test flash_ctrl_host_ctrl_arb has 1 failures.
  - 0.flash_ctrl_host_ctrl_arb.83844780297281522890863939002545391056795083101694502148311362427356931089798
    Log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_error_prog_type has 1 failures.
  - 0.flash_ctrl_error_prog_type.65848615336298306627746327556981645600396458835499191731809176006022198201825
    Log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_rw has 2 failures.
  - 4.flash_ctrl_rw.104835213269947667885955088274210632178452980181290485532145617802998212631061
    Log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```
  - 10.flash_ctrl_rw.114768897555900819699858121251781742493101131508690048949235218611906846459940
    Log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 4.flash_ctrl_intr_wr_slow_flash.109019671695901140380001009385688819781144614037983725408977883090759842133017
    Log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 28.flash_ctrl_prog_reset.35449622461093970919167627307199742348496091635326771050981909897186451340748
    Log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest/run.log
```
  Job timed out after 60 minutes
```
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 2 failures:
- Test flash_ctrl_phy_host_grant_err has 2 failures.
  - 0.flash_ctrl_phy_host_grant_err.54416620414219778981797580492174253955889463043525425991830923813647824830505
    Line 112, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 14751.5 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 14751.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 4.flash_ctrl_phy_host_grant_err.107649005119267824876445755402305296008473441029433040682959287114073855389221
    Line 112, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 19968.9 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 19968.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue has 2 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.36285965157771438262536703321071198756408147367446416835949450216306375041818
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue
  UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_wo has 1 failures.
  - 19.flash_ctrl_wo.114785698748733347599825451602511963992060565814530125334446376618165730003791
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest/run.log
```
  UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue
  UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 17.flash_ctrl_ro.90828062815792684608942431776556182806811700189199486323300318553316319810661
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 101724.0 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 101724.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```