FLASH_CTRL Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.752m	689.116us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	54.590s	50.897us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.004m	280.690us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	26.540s	109.208us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.516m	17.281ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.042m	2.526ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	33.110s	39.635us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	26.540s	109.208us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	2.526ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	21.670s	29.399us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	28.590s	31.864us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	52.020s	32.344us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	3.226m	125.664us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.273m	95.820ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.964m	350.239ms	20	20	100.00
		flash_ctrl_lcmgr_intg	29.300s	58.683us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	50.960m	268.013ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.575m	5.612ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.091m	2.360ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.117h	50.873ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.753m	1.409ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.035m	27.606us	39	40	97.50
		flash_ctrl_rw_evict_all_en	1.028m	43.698us	39	40	97.50
		flash_ctrl_re_evict	1.130m	88.704us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.843m	1.425ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.843m	1.425ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	7.600m	4.750ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	47.250s	1.150ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	26.174m	1.253ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	55.966m	29.141ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	24.119m	366.294us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	52.308m	683.811us	4	5	80.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	29.000s	16.014us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.201m	6.667ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	44.820s	10.486us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	33.130s	47.639us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	20.691m	755.384us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.708m	3.140ms	50	50	100.00
		flash_ctrl_otp_reset	4.197m	132.665us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.273m	95.820ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.604m	8.848ms	39	40	97.50
		flash_ctrl_intr_wr	2.115m	17.378ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	9.095m	78.032ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	12.004m	217.767ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.932m	4.030ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.874m	672.598us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	46.620s	32.125us	5	5	100.00
		flash_ctrl_ro_derr	3.039m	2.687ms	10	10	100.00
		flash_ctrl_rw_derr	33.826m	200.000ms	9	10	90.00
		flash_ctrl_derr_detect	4.397m	1.229ms	5	5	100.00
		flash_ctrl_integrity	9.583m	8.248ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	44.890s	308.034us	5	5	100.00
		flash_ctrl_ro_serr	2.808m	781.808us	10	10	100.00
		flash_ctrl_rw_serr	4.603m	2.074ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.859m	6.464ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	2.009m	4.809ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.231m	5.005ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.810s	73.357us	1	1	100.00
		flash_ctrl_read_word_sweep	15.760s	48.283us	1	1	100.00
		flash_ctrl_ro	2.420m	754.995us	19	20	95.00
		flash_ctrl_rw	9.292m	18.430ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	57.670s	1.147ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.631m	446.865ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	6.332m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	30.550s	119.571us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	24.440s	19.218us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	28.720s	190.431us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	28.720s	190.431us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.004m	280.690us	5	5	100.00
		flash_ctrl_csr_rw	26.540s	109.208us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	2.526ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	51.570s	1.918ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.004m	280.690us	5	5	100.00
		flash_ctrl_csr_rw	26.540s	109.208us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	2.526ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	51.570s	1.918ms	20	20	100.00
V2		TOTAL			1005	1013	99.21
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	28.980s	17.341us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	28.980s	17.341us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	28.980s	17.341us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	28.980s	17.341us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	31.790s	37.822us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
		flash_ctrl_tl_intg_err	25.077m	660.363us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	25.077m	660.363us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	25.077m	660.363us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	59.500s	208.518us	3	3	100.00
		flash_ctrl_wr_intg	30.740s	45.777us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.752m	689.116us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.197m	132.665us	80	80	100.00
		flash_ctrl_disable	44.820s	10.486us	50	50	100.00
		flash_ctrl_sec_info_access	1.895m	1.642ms	50	50	100.00
		flash_ctrl_connect	33.130s	47.639us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	25.900s	20.960us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	26.540s	109.208us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.980s	17.341us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	26.540s	109.208us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.980s	17.341us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	26.540s	109.208us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	28.980s	17.341us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	44.820s	10.486us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	59.500s	208.518us	3	3	100.00
		flash_ctrl_access_after_disable	24.770s	40.895us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	42.790s	28.026us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	44.820s	10.486us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	47.250s	1.150ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.292m	18.430ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.603m	2.074ms	10	10	100.00
		flash_ctrl_rw_derr	33.826m	200.000ms	9	10	90.00
		flash_ctrl_integrity	9.583m	8.248ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.273m	95.820ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	35.060s	696.296us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	29.140s	15.624us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	29.690s	15.605us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.917h	4.040ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.517m	87.263us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1281	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.27	95.73	93.97	98.31	92.52	98.27	96.89	98.21

Failure Buckets

Job timed out after * minutes has 2 failures:
- Test flash_ctrl_intr_wr has 1 failures.
  - 0.flash_ctrl_intr_wr.28325475749964958778045917484519380334786930331021582183950620004508738502623
    Log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_error_prog_type has 1 failures.
  - 2.flash_ctrl_error_prog_type.5528404032409707725771214752931716176853642595309311122868073756454602094975
    Log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 15.flash_ctrl_rw_evict.33394868874667393840009044201756178698479938072409945396202215932363767073181
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 55606.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 55606.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 18.flash_ctrl_rw_evict_all_en.81450709485101290042200686338517815333939319164890100863070885170917072962323
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 19348.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 19348.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 4.flash_ctrl_rw_derr.76902116078629241253676853442154687752165427055451647885037831863842050048595
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue
  UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw has 1 failures.
  - 8.flash_ctrl_rw.10630715262357730471481213519379879137718736210937350637803447137390340102591
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 1867320.8 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 1867320.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp b6c8bca1_e37d8028:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 9.flash_ctrl_intr_rd.6667609924226865632203182212101484628985454697198767856123925650734062004044
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 3123185.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    b6c8bca1_e37d8028:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 3123185.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 15.flash_ctrl_ro.63427417499365379399215193140963989996487782428999266724213489012199302294849
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 30830.5 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 30830.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`