FLASH_CTRL Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.131m	11.250ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	44.930s	19.494us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.278m	126.338us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	33.040s	27.167us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	2.403m	13.702ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.249m	873.883us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	37.890s	228.929us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	33.040s	27.167us	20	20	100.00
		flash_ctrl_csr_aliasing	1.249m	873.883us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	26.820s	14.303us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	26.610s	16.208us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	51.690s	96.415us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	3.960m	69.012us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.462m	337.638ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.196m	190.223ms	20	20	100.00
		flash_ctrl_lcmgr_intg	26.470s	27.406us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.088m	251.942ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	11.287m	37.242ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.902m	10.045ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.053h	65.545ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.504m	1.409ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	58.200s	138.026us	39	40	97.50
		flash_ctrl_rw_evict_all_en	1.010m	70.380us	39	40	97.50
		flash_ctrl_re_evict	1.110m	73.714us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	15.025m	3.341ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	15.025m	3.341ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.410m	56.298ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	47.490s	1.442ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	30.417m	7.719ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	55.693m	3.928ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	24.193m	957.572us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	57.553m	2.043ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	29.030s	109.147us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.164m	1.825ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	44.400s	20.698us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.340s	45.457us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	37.494m	680.980us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.094m	3.310ms	50	50	100.00
		flash_ctrl_otp_reset	4.366m	245.342us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.462m	337.638ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.517m	8.368ms	38	40	95.00
		flash_ctrl_intr_wr	1.774m	5.019ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.800m	49.225ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.792m	24.489ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.850m	2.178ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.318m	649.346us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	46.750s	32.730us	5	5	100.00
		flash_ctrl_ro_derr	3.201m	3.028ms	10	10	100.00
		flash_ctrl_rw_derr	3.932m	5.048ms	9	10	90.00
		flash_ctrl_derr_detect	5.476m	790.726us	5	5	100.00
		flash_ctrl_integrity	9.393m	3.610ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	44.840s	48.980us	5	5	100.00
		flash_ctrl_ro_serr	3.022m	1.229ms	10	10	100.00
		flash_ctrl_rw_serr	3.906m	22.341ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.713m	1.639ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.762m	1.024ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.605m	11.707ms	19	20	95.00
		flash_ctrl_write_word_sweep	17.850s	151.747us	1	1	100.00
		flash_ctrl_read_word_sweep	21.830s	22.555us	1	1	100.00
		flash_ctrl_ro	2.516m	540.370us	20	20	100.00
		flash_ctrl_rw	9.880m	4.575ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	1.005m	4.632ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.365m	62.553ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.251m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	29.560s	139.144us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	28.090s	14.934us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	36.260s	60.572us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	36.260s	60.572us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.278m	126.338us	5	5	100.00
		flash_ctrl_csr_rw	33.040s	27.167us	20	20	100.00
		flash_ctrl_csr_aliasing	1.249m	873.883us	5	5	100.00
		flash_ctrl_same_csr_outstanding	1.130m	844.808us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.278m	126.338us	5	5	100.00
		flash_ctrl_csr_rw	33.040s	27.167us	20	20	100.00
		flash_ctrl_csr_aliasing	1.249m	873.883us	5	5	100.00
		flash_ctrl_same_csr_outstanding	1.130m	844.808us	20	20	100.00
V2		TOTAL			1006	1013	99.31
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	30.820s	17.726us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	30.820s	17.726us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	30.820s	17.726us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	30.820s	17.726us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	31.590s	13.581us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
		flash_ctrl_tl_intg_err	27.170m	968.745us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	27.170m	968.745us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	27.170m	968.745us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	47.660s	978.224us	3	3	100.00
		flash_ctrl_wr_intg	30.400s	46.794us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.131m	11.250ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.366m	245.342us	80	80	100.00
		flash_ctrl_disable	44.400s	20.698us	50	50	100.00
		flash_ctrl_sec_info_access	1.939m	6.042ms	50	50	100.00
		flash_ctrl_connect	32.340s	45.457us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	25.750s	39.275us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	33.040s	27.167us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	30.820s	17.726us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	33.040s	27.167us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	30.820s	17.726us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	33.040s	27.167us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	30.820s	17.726us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	44.400s	20.698us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	47.660s	978.224us	3	3	100.00
		flash_ctrl_access_after_disable	28.180s	42.966us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	42.190s	28.404us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	44.400s	20.698us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	47.490s	1.442ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.880m	4.575ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	3.906m	22.341ms	10	10	100.00
		flash_ctrl_rw_derr	3.932m	5.048ms	9	10	90.00
		flash_ctrl_integrity	9.393m	3.610ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.462m	337.638ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	38.820s	825.468us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	28.640s	45.005us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	27.350s	10.476us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.000h	2.765ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.224m	38.106us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1281	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	95.26	93.87	98.31	92.52	97.21	96.89	98.18

Failure Buckets

• Job timed out after * minutes has 3 failures:

  • Test flash_ctrl_rw_derr has 1 failures.

    • 4.flash_ctrl_rw_derr.46954233555168868951093861651958766220979182175593535897212059202194316016621
      Log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_rw has 1 failures.

    • 10.flash_ctrl_rw.16405042514997213686419973758147792864352762472728935600041947885481025577451
      Log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_wo has 1 failures.

    • 11.flash_ctrl_wo.30546671867621870369092407257542434043607875094694183389064230536875066334657
      Log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 15.flash_ctrl_rw_evict.36149413740645682317062946547777139403897192270313565702600462210725934200906
      Line 95, in log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 47237.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 47237.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 19.flash_ctrl_rw_evict_all_en.2952209903330142167589537089239184235672592203709179403966929802139477481869
      Line 95, in log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 40062.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 40062.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test flash_ctrl_phy_ack_consistency has 1 failures.

    • 3.flash_ctrl_phy_ack_consistency.77359018369656612244463010000239643372777629714714948823899160716688678800034
      Line 97, in log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest/run.log

        UVM_ERROR @ 10475.8 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x2)
        UVM_INFO @ 10475.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e80f56d_1e138ca7:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 22.flash_ctrl_intr_rd.11629310242340506474262196001632577356163516660869967739437287266611708237550
      Line 95, in log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 330336.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    6e80f56d_1e138ca7:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 330336.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp a02a0953_3a7f9f70:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 25.flash_ctrl_intr_rd.109910563140956849126793929595387650810417841465813410423012728485987209353952
      Line 95, in log /workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 3818607.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    a02a0953_3a7f9f70:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 3818607.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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