Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25874508	1		T1	396		T2	3422		T3	15
full_word	7868200	1		T1	149		T2	4586		T3	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33742388	1		T1	545		T2	8008		T3	18
auto[TlIntgErrCmd]	108	1		T65	7		T184	12		T185	5
auto[TlIntgErrData]	105	1		T65	3		T184	5		T185	3
auto[TlIntgErrBoth]	107	1		T65	10		T184	3		T185	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29277927	1		T1	451		T2	3098		T3	14
auto[1]	4464781	1		T1	94		T2	4910		T3	4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25152260	1		T1	380		T2	3097		T3	14
auto[TlIntgErrNone]	partial	auto[1]	721954	1		T1	16		T2	325		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	4125523	1		T1	71		T2	1		T4	1667
auto[TlIntgErrNone]	full_word	auto[1]	3742651	1		T1	78		T2	4585		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	47	1		T65	1		T184	6		T185	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T65	4		T184	5		T185	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T184	1		T280	1		T363	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T65	2		T185	1		T363	1
auto[TlIntgErrData]	partial	auto[0]	51	1		T65	1		T184	2		T185	1
auto[TlIntgErrData]	partial	auto[1]	47	1		T65	2		T184	2		T185	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T252	1		T280	1		T281	2
auto[TlIntgErrData]	full_word	auto[1]	2	1		T184	1		T363	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T65	5		T184	1		T185	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T65	4		T184	1		T245	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T280	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1		T65	1		T184	1		T185	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22112	1		T65	18		T186	507		T184	17
full_word	4012363	1		T1	6		T3	10		T4	89

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4034170	1		T1	6		T3	10		T4	89
auto[TlIntgErrCmd]	88	1		T65	8		T184	7		T185	4
auto[TlIntgErrData]	122	1		T65	6		T184	7		T185	5
auto[TlIntgErrBoth]	95	1		T65	5		T184	4		T185	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4007387	1		T1	6		T3	10		T4	89
auto[1]	27088	1		T65	11		T186	599		T184	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1236	1		T186	23		T231	62		T232	5
auto[TlIntgErrNone]	partial	auto[1]	20594	1		T186	484		T231	1061		T232	92
auto[TlIntgErrNone]	full_word	auto[0]	4006007	1		T1	6		T3	10		T4	89
auto[TlIntgErrNone]	full_word	auto[1]	6333	1		T186	115		T231	603		T232	28
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T65	3		T184	2		T185	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T65	5		T184	5		T185	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T364	1		T365	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T248	1		T366	1		-	-
auto[TlIntgErrData]	partial	auto[0]	61	1		T65	2		T184	4		T185	2
auto[TlIntgErrData]	partial	auto[1]	49	1		T65	3		T184	2		T185	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T184	1		T252	2		T280	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T65	1		T248	1		T362	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T65	3		T184	2		T245	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T65	2		T184	2		T185	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T245	1		T252	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T253	1		T280	1		T367	1